Layered heater system having conductive overlays

US11304265B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11304265-B2
Application numberUS-201816157664-A
CountryUS
Kind codeB2
Filing dateOct 11, 2018
Priority dateJul 20, 2006
Publication dateApr 12, 2022
Grant dateApr 12, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of manufacturing a layered heater includes: applying a dielectric material on a substrate to form a dielectric layer; thermal-spraying a resistive material on the dielectric layer to form a resistive layer on the dielectric layer; forming a plurality of conductive overlays at predetermined locations on the substrate; and forming a plurality of cuts into the resistive layer by laser cutting to form a resistive circuit pattern that overlaps the conductive overlays.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of manufacturing a layered heater, comprising: applying a dielectric material on a substrate to form a dielectric layer; thermally spraying a resistive material on the dielectric layer to form a resistive layer on the dielectric layer; forming a plurality of conductive overlays at predetermined locations on the substrate; and forming a plurality of cuts into the resistive layer by laser cutting to form a resistive circuit pattern that overlaps the conductive overlays. 2. The method according to claim 1 , wherein the substrate defines opposing ends, and the forming of a plurality of conductive overlays comprises forming the plurality of conductive overlays along each of the opposing ends of the substrate. 3. The method according to claim 1 , wherein the plurality of conductive overlays are discretely arranged along each of opposing ends of the substrate before the resistive circuit pattern is formed. 4. The method according to claim 1 , wherein the resistive circuit pattern includes a plurality of bend portions. 5. The method according to claim 4 , wherein the plurality of conductive overlays overlap the bend portions. 6. The method according to claim 5 , wherein the conductive overlays are formed on at least one of a top surface and a bottom surface of the bend portions. 7. The method according to claim 1 , wherein some of the plurality of cuts are parallel. 8. The method according to claim 7 , wherein the plurality of cuts extend between the plurality of conductive overlays. 9. The method according to claim 1 , wherein the resistive layer is a continuous resistive layer disposed on an entire surface of the dielectric layer. 10. The method according to claim 1 , wherein the conductive overlays have a variable thickness. 11. The method according to claim 1 , wherein the plurality of cuts do not extend longitudinally into the conductive overlays. 12. The method according to claim 11 , wherein ends of the plurality of cuts are disposed outside the conductive overlays. 13. The method according to claim 1 , further comprising making the plurality of cuts into a portion of the dielectric layer such that a thickness of a portion of the dielectric layer overlapping the conductive overlays is larger than a thickness of another portion of the dielectric layer not overlapping the conductive overlays. 14. The method according to claim 1 , wherein the plurality of cuts extend through the resistive layer between the conductive overlays and longitudinally into a portion of the conductive overlays such that no portion of the resistive pattern is present outside the conductive overlay proximate the end of the plurality of cuts and opposing ends of each cut being disposed at areas where the conductive overlays are disposed. 15. The method according to claim 1 , further comprising cutting the resistive layer to divide the resistive layer into the resistive circuit pattern and at least one intermediate area spaced apart from the resistive heating pattern. 16. The method according to claim 15 , wherein the intermediate area is electrically inactive. 17. A method of manufacturing a layered heater, comprising: applying a dielectric material on a substrate to form a dielectric layer; depositing a resistive material on the dielectric layer by a layered process selected from a group consisting of thick film, thin film, thermal spray, and sol gel to form a resistive layer in the form of a coating on the dielectric layer; forming a plurality of conductive overlays by the layered process at predetermined locations on the substrate; and forming a plurality of cuts into the resistive layer to form a resistive circuit pattern. 18. The method according to claim 17 , wherein the plurality of cuts are formed by laser cutting. 19. A method of manufacturing a layered heater, comprising: forming a continuous resistive layer on a substrate, the substrate defining opposing ends; forming a plurality of conductive overlays at predetermined locations along each of the opposing ends of the substrate; and forming a plurality of cuts into the continuous resistive layer to form a resistive circuit pattern such that the resistive circuit pattern defines a plurality of bend portions proximate the conductive overlays. 20. The method according to claim 19 , wherein the plurality of conductive overlays are formed before the plurality of cuts are formed.

Assignees

Inventors

Classifications

  • Heaters using resistive films or coatings · CPC title

  • H05B3/20Primary

    Heating elements having extended surface area substantially in a two-dimensional [2D] plane, e.g. plate-heater (H05B3/62, H05B3/68, H05B3/78, H05B3/84 take precedence) · CPC title

  • Heaters comprising a particular structure with multiple layers · CPC title

  • by laser · CPC title

  • using serpentine layout · CPC title

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Frequently asked questions

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What does patent US11304265B2 cover?
A method of manufacturing a layered heater includes: applying a dielectric material on a substrate to form a dielectric layer; thermal-spraying a resistive material on the dielectric layer to form a resistive layer on the dielectric layer; forming a plurality of conductive overlays at predetermined locations on the substrate; and forming a plurality of cuts into the resistive layer by laser cut…
Who is the assignee on this patent?
Watlow Electric Mfg
What technology area does this patent fall under?
Primary CPC classification H05B3/20. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 12 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).