Display panel with lens structure on pixel definition layer

US11302899B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11302899-B2
Application numberUS-201916631546-A
CountryUS
Kind codeB2
Filing dateOct 17, 2019
Priority dateJul 5, 2019
Publication dateApr 12, 2022
Grant dateApr 12, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display panel is provided, which includes an array substrate, a pixel definition layer disposed on the array substrate, and a light-transmitting region disposed on a side of the array substrate away from the pixel definition layer. The pixel definition layer is provided with a first hole corresponding to a position of the light-transmitting region, and the pixel definition layer is provided with at least one convex lens structure near an edge of the first hole.

First claim

Opening claim text (preview).

What is claimed is: 1. A display panel, comprising: an array substrate; a pixel definition layer disposed on the array substrate; a light-transmitting region disposed on a side of the array substrate away from the pixel definition layer; wherein the pixel definition layer is provided with a first hole corresponding to a position of the light-transmitting region, and the pixel definition layer is provided with at least one first recess near an edge of the first hole, and the at least one first recess is filled with a transparent material to form at least one convex lens structure. 2. The display panel according to claim 1 , wherein a maximum height of the at least one convex lens structure is greater than a maximum depth of the corresponding first recess. 3. The display panel according to claim 1 , wherein the first hole is a pixel opening in the pixel definition layer. 4. The display panel according to claim 1 , wherein the array substrate is provided with a second hole corresponding to the position of the light-transmitting region, and the second hole is connected to the first hole. 5. The display panel according to claim 4 , wherein the array substrate comprises a substrate and a thin film transistor layer disposed on the array substrate, the pixel definition layer is disposed on the thin film transistor layer, the second hole is disposed in the thin film transistor layer, and the light-transmitting region is a second recess disposed on a side of the substrate away from the thin film transistor layer. 6. The display panel according to claim 5 , further comprising a plurality of anodes spaced apart on the thin film transistor layer, wherein the pixel definition layer is disposed on the plurality of anodes and on the thin film transistor layer between the plurality of anodes, the first hole is disposed in the pixel definition layer between two adjacent anodes, and the second hole is disposed in the thin film transistor layer between two adjacent anodes. 7. The display panel according to claim 5 , wherein the thin film transistor layer comprises a buffer layer, an active layer, a gate insulating layer, a gate electrode, an interlayer insulating layer, source/drain electrodes, and a planarization layer sequentially disposed on the substrate, and the second hole is extended through the planarization layer. 8. The display panel according to claim 7 , further comprising a light-emitting layer, a cathode, and a transparent layer, wherein the light-emitting layer is disposed on the pixel definition layer, the anode, the convex lens structure, and the interlayer insulating layer at a bottom of the second hole, the cathode is disposed on the light-emitting layer, and the transparent layer is disposed on the cathode and the first hole and the second hole are filled with the transparent layer. 9. The display panel according to claim 1 , further comprising a black matrix disposed on a side of the pixel definition layer away from the array substrate, wherein the black matrix is provided with a third hole corresponding to the position of the first hole, and the third hole is filled with a transparent material. 10. A display panel, comprising: an array substrate; a pixel definition layer disposed on the array substrate; a light-transmitting region disposed on a side of the array substrate away from the pixel definition layer, wherein the pixel definition layer is provided with a first hole corresponding to a position of the light-transmitting region, and the pixel definition layer is provided with at least one convex lens structure near an edge of the first hole. 11. The display panel according to claim 10 , wherein the first hole is a pixel opening in the pixel definition layer. 12. The display panel according to claim 10 , wherein the array substrate is provided with a second hole corresponding to the position of the light-transmitting region, and the second hole is connected to the first hole. 13. The display panel according to claim 12 , wherein the array substrate comprises a substrate and a thin film transistor layer disposed on the array substrate, the pixel definition layer is disposed on the thin film transistor layer, the second hole is disposed in the thin film transistor layer, and the light-transmitting region is a second recess disposed on a side of the substrate away from the thin film transistor layer. 14. The display panel according to claim 13 , further comprising a plurality of anodes spaced apart on the thin film transistor layer, wherein the pixel definition layer is disposed on the plurality of anodes and on the thin film transistor layer between the plurality of anodes, the first hole is disposed in the pixel definition layer between two adjacent anodes, and the second hole is disposed in the thin film transistor layer between two adjacent anodes. 15. The display panel according to claim 13 , wherein the thin film transistor layer comprises a buffer layer, an active layer, a gate insulating layer, a gate electrode, an interlayer insulating layer, source/drain electrodes, and a planarization layer sequentially disposed on the substrate, and the second hole is extended through the planarization layer. 16. The display panel according to claim 15 , further comprising a light-emitting layer, a cathode, and a transparent layer, wherein the light-emitting layer is disposed on the pixel definition layer, the anode, the convex lens structure, and the interlayer insulating layer at a bottom of the second hole, the cathode is disposed on the light-emitting layer, and the transparent layer is disposed on the cathode and the first hole and the second hole are filled with the transparent layer. 17. The display panel according to claim 10 , further comprising a black matrix disposed on a side of the pixel definition layer away from the array substrate, wherein the black matrix is provided with a third hole corresponding to the position of the first hole, and the third hole is filled with a transparent material.

Assignees

Inventors

Classifications

  • comprising light absorbing layers, e.g. black layers · CPC title

  • comprising refractive means, e.g. lenses · CPC title

  • OLEDs integrated with inorganic image sensors · CPC title

  • comprising refractive means, e.g. lenses · CPC title

  • H10K59/122Primary

    Pixel-defining structures or layers, e.g. banks · CPC title

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What does patent US11302899B2 cover?
A display panel is provided, which includes an array substrate, a pixel definition layer disposed on the array substrate, and a light-transmitting region disposed on a side of the array substrate away from the pixel definition layer. The pixel definition layer is provided with a first hole corresponding to a position of the light-transmitting region, and the pixel definition layer is provided w…
Who is the assignee on this patent?
Wuhan China Star Optoelectronics Semiconductor Display Tech Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10K59/122. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 12 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).