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Using programmable switching chips as artificial neural networks engines
US11301751B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11301751-B2 |
| Application number | US-201715724281-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 4, 2017 |
| Priority date | Oct 4, 2017 |
| Publication date | Apr 12, 2022 |
| Grant date | Apr 12, 2022 |
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Abstract
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A method for executing a binarized neural network (BNN) using a switching chip includes describing an artificial neural network application in a binarized form to provide the BNN; configuring a parser of the switching chip to encode an input vector of the BNN in a packet header; configuring a plurality of match-action tables (MATs) of the switching chip to execute, on the input vector encoded in the packet header, one or more of the operations including XNOR, bit counting, and sign operations such that the plurality of MATs are configured to: implement a bitwise XNOR operation between the input vector and a weights matrix to produce a plurality of first stage vectors, implement an algorithm for counting a number of bits set to 1 in the plurality of first stage vectors to produce a plurality of second stage vectors, and implement a sign operation on the second stage vectors.
First claim
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What is claimed is: 1. A method for executing a binarized neural network (BNN) using a switching chip, the method comprising: describing an artificial neural network application in a binarized form to provide the BNN; configuring a parser of the switching chip to encode an input vector of the BNN in a packet header; configuring a plurality of match-action tables (MATs) of the switching chip to execute, on the input vector encoded in the packet header, one or more of the operat…
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- What does patent US11301751B2 cover?
- A method for executing a binarized neural network (BNN) using a switching chip includes describing an artificial neural network application in a binarized form to provide the BNN; configuring a parser of the switching chip to encode an input vector of the BNN in a packet header; configuring a plurality of match-action tables (MATs) of the switching chip to execute, on the input vector encoded i…
- Who is the assignee on this patent?
- Nec Europe Ltd, Nec Corp
- What technology area does this patent fall under?
- Primary CPC classification G06N3/04. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Apr 12 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).