Method and apparatus for characterizing workload sequentiality for cache policy optimization

Patent metadata

Field	Value
Publication number	US-11301395-B2
Application number	US-201916678197-A
Country	US
Kind code	B2
Filing date	Nov 8, 2019
Priority date	Nov 8, 2019
Publication date	Apr 12, 2022
Grant date	Apr 12, 2022

Abstract

A method for characterizing workload sequentiality for cache policy optimization includes maintaining an IO trace data structure having a rolling window of IO traces describing access operations on addresses of a storage volume. A page count data structure is maintained that includes a list of all of the addresses of the storage volume referenced by the IO traces in the IO trace data structure. A list of sequences data structure is maintained that contains a list of all sequences of the addresses of the storage volume that were accessed by the IO traces in the IO trace data structure. A sequence lengths data structure is used to correlate each sequence in the list of sequences data structure with a length of the sequence, and a histogram data structure is used to correlate sequence lengths and a number of how many of sequences of each length are maintained in the sequence lengths data structure.

First claim

What is claimed is:

1. A method for optimizing performance of a storage system, the storage system having a cache and a cache management system controlling operation of the cache, the method comprising the steps of:
maintaining, by the cache management system, an IO trace data structure having a rolling window of IO traces describing access operations on addresses of a storage volume;
maintaining, by the cache management system, a page count data structure having a list of all of the addresses of the storage volume referenced by the IO traces in the IO trace data structure;
maintaining, by the cache management system, a list of sequences data structure containing sequences of the addresses of the storage volume referenced by the IO traces in the IO trace data structure;
maintaining, by the cache management system, a sequence lengths data structure correlating each sequence in the list of sequences data structure with a length of the sequence; and
maintaining, by the cache management system, a histogram data structure correlating sequence lengths and a number of how many of sequences of that length are maintained in the sequence lengths data structure; and
adjusting a cache policy applied to the cache to adjust operation of the cache, by the cache management system, based on the content of the histogram data structure.

2. The method of claim 1 , wherein the list of sequences data structure is a double linked list of the sequences of the addresses of the storage volume referenced by the IO traces in the IO trace data structure, with duplicate addresses removed.

3. The method of claim 2 , wherein list of sequences data structure is an ordered list of sequences based on a head address of each sequence, and wherein each sequence other than a first sequence and last sequence, has a respective first pointer to a previous sequence in the list of sequences data structure and a respective second pointer to a subsequent sequence in the list of sequences data structure.

4. The method of claim 1 , further comprising updating the IO trace data structure to remove a first IO trace from the rolling window of IO traces.

5. The method of claim 4 , further comprising updating the page count data structure to decrement a page count of a first address associated with the removed first IO trace.

6. The method of claim 5 , wherein when a result of decrementing the page count of the first address causes the page count for the first address to be equal to zero, the method further comprising updating the list of sequences data structure to remove the first address from a first sequence containing the first address.

7. The method of claim 6 , further comprising updating the sequence lengths data structure after removing the first address from the list of sequences data structure; and updating the histogram data structure after removing the first address from the list of sequences data structure.

8. The method of claim 6 , wherein when the first address is intermediate a head address of the first sequence and a tail address of the first sequence, and removal of the first address causes a pair of adjacent addresses in the sequence to be greater than a gap distance away from each other, the step of updating the list of sequences data structure comprises creating two new sequences from the first sequence.

9. The method of claim 8 , wherein a first of the two new sequence includes all elements of the first sequence before the removed first address and a second of the two new sequence comprises all the elements of the first sequence after the removed first address.

10. The method of claim 1 , further comprising updating the IO trace data structure to insert a second IO trace into the rolling window of IO traces.

11. The method of claim 10 , further comprising updating the page count data structure to increment a page count of a second address associated with the inserted second IO trace.

12. The method of claim 11 , wherein when a result of incrementing the page count of the second address causes the page count for the second address to be equal to one, the method further comprising determining a correct place to insert the second address in the list of sequences data structure.

13. The method of claim 12 , wherein when the correct place to insert the second address in the list of sequences data structure is in a middle of a previous sequence contained by the list of sequences data structure, performing an insert procedure to add the second address to the previous sequence.

14. The method of claim 12 , wherein when the correct place to insert the second address in the list of sequences data structure is in between two previous sequences contained by the list of sequences data structure, performing an insert procedure to add the second address as a new sequence in the list of sequences data structure.

15. The method of claim 12 , further comprising updating the sequence lengths data structure after inserting the second address into the list of sequences data structure.

16. The method of claim 15 , further comprising updating the histogram data structure after inserting the second address into the list of sequences data structure.

17. The method of claim 12 , wherein when the correct place to insert the second address in the list of sequences data structure is at a head or tail of a first of the previous sequences contained by the list of sequences data structure, performing an insert procedure to add the second address as a new head address or new tail address of the first of the previous sequences in the list of sequences data structure.

18. The method of claim 17 , wherein when the second address is inserted as the new head address of the first of the previous sequences in the list of sequences data structure, and the second address is less than a gap distance away from a tail address of a second of the previous sequences in the list of sequences data structure, the method further comprising the step of joining the first of the previous sequences and the second of the previous sequences in the list of sequences data structure.

19. The method of claim 17 , wherein when the second address is inserted as the new tail address of the first of the previous sequences in the list of sequences data structure, and the second address is less than a gap distance away from a head address of a second of the previous sequences in the list of sequences data structure, the method further comprising the step of joining the first of the previous sequences and the second of the previous sequences in the list of sequences data structure.

Assignees

• Emc Ip Holding Co Llc
• Dell Products Lp

Inventors

• Barbalho Hugo De Oliveira
• Gottin Vinícius Michel
• Pinho Rômulo Teixeira De Abreu

Classifications

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F12/122 Primary

  of the least frequently used [LFU] type, e.g. with individual count value · CPC title

• G06F3/061 Primary

  Improving I/O performance · CPC title

• G06F3/0656

  Data buffering arrangements · CPC title

• G06F16/2379

  Updates performed during online database operations; commit processing · CPC title