System and method for handling floating point hardware exception

Patent metadata

Field	Value
Publication number	US-11301247-B2
Application number	US-202016864069-A
Country	US
Kind code	B2
Filing date	Apr 30, 2020
Priority date	Dec 19, 2019
Publication date	Apr 12, 2022
Grant date	Apr 12, 2022

Abstract

A method includes receiving an input data at a FP arithmetic operating unit configured to perform a FP arithmetic operation on the input data. The method further includes determining whether the received input data generates a FP hardware exception responsive to the FP arithmetic operation on the input data, wherein the determining occurs prior to performing the FP arithmetic operation. The method also includes converting a value of the received input data to a modified value responsive to the determining that the received input data generates the FP hardware exception, wherein the converting eliminates generation of the FP hardware exception responsive to the FP arithmetic operation on the input data.

First claim

What is claimed is:

1. A computer-implemented method comprising:
receiving an input data at a floating point arithmetic operating unit, wherein the floating point operating unit is configured to perform a floating point arithmetic operation on the input data;
determining whether the received input data generates a floating point hardware exception responsive to the floating point arithmetic operation on the input data, wherein the determining occurs prior to performing the FP arithmetic operation; and
converting a value of the received input data to a modified value responsive to the determining that the received input data generates the floating point hardware exception, wherein the converting eliminates generation of the floating point hardware exception responsive to the floating point arithmetic operation on the input data, wherein the modified value for the input data is a maximum supported value if the input data is positive infinity and wherein the modified value for the input data is a minimum supported value if the input data is negative infinity.

2. The method of claim 1 further comprising performing the floating point arithmetic operation on the input data with modified value to generate an output result.

3. The method of claim 2 , wherein the floating point arithmetic operation is selected from one of an addition operation, a subtraction operation, or an add-reduce operation.

4. The method of claim 2 further comprising determining whether the output result of the FP arithmetic operation generates a floating point hardware exception.

5. The method of claim 4 further comprising setting a value of the output result to zero if a value of the output result is a denormal number.

6. The method of claim 4 further comprising setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity, and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.

7. The method of claim 1 further comprising setting a value of the input data to zero if the input data is a denormal number.

8. The method of claim 7 further comprising generating an out-of-bounds flag associated with the denormal number.

9. The method of claim 1 further comprising generating an out-of-bounds flag associated with the input data.

10. The method of claim 1 further comprising generating an out-of-bounds flag associated with the input data.

11. The method of claim 1 further comprising setting a value of the input data to zero if the input data is a qnan (quiet not-a-number).

12. The method of claim 11 further comprising generating an un-initialized flag associated with the input data.

13. The method of claim 1 , wherein the input data is an snan (signaling not-a-number) and wherein the modified value is zero.

14. The method of claim 13 further generating an un-initialized flag associated with the input data.

15. A computer-implemented method comprising:
receiving a first input data at a floating point arithmetic operating unit for a FP arithmetic operation;
receiving a second input data at the floating point arithmetic operating unit for the floating point operation;
generating an out-of-bounds flag associated with the input data if the input data is positive infinity or negative infinity;
eliminating a floating point hardware exception responsive to the floating point arithmetic operation on the first and the second input data by performing one or more of: setting the first input data to zero if the first input data is a denormal number, a qnan (quiet not-a-number), or an snan (signaling not-a-number);
setting the first input data to a maximum supported value if the first input data is positive infinity;
setting the first input data to a minimum supported value if the first input data is a negative infinity;
setting the second input data to zero if the second input data is a denormal number, a qnan, or an snan;
setting the second input data to the maximum supported value if the second input data is positive infinity; and
setting the second input data to the minimum supported value if the second input data is a negative infinity.

16. The method of claim 15 further comprising performing the floating point arithmetic operation on the first and the second input data or their modified values to generate an output result.

17. The method of claim 16 , wherein the floating point arithmetic operation is selected from one of an addition operation, a subtraction operation, or an add-reduce operation.

18. The method of claim 16 further comprising setting a value of the output result to zero if a value of the output result is a denormal number.

19. The method of claim 16 further comprising setting a value of the output result to the maximum supported number if a value of the output result is a positive infinity, and setting a value of the output result to the minimum supported number if a value of the output result is a negative infinity.

20. The method of claim 15 further comprising generating an out-of-bounds flag associated with the denormal number.

21. The method of claim 15 further comprising generating an un-initialized flag associated with qnan input data.

22. The method of claim 15 further generating an un-initialized flag associated with snan input data.

23. A system comprising:
a logic engine configured to receive an input data for arithmetic operation to be operated on by a floating point arithmetic operating unit, wherein the logic engine is configured to determine whether the received input data generates a floating point hardware exception responsive to the floating point arithmetic operation on the input data, wherein the determining occurs prior to performing the floating point arithmetic operation; and
a convertor engine configured to convert a value of the received input data to a modified value responsive to the determining that the received input data generates the floating point hardware exception, wherein the converting eliminates generation of the FP hardware exception responsive to the floating point arithmetic operation on the input data wherein the modified value for the input data is a maximum supported value if the input data is positive infinity and wherein the modified value for the input data is a minimum supported value if the input data is negative infinity.

24. The system of claim 23 further comprising an arithmetic floating point operator configured to perform the floating point arithmetic operation on the input data with modified value to generate an output result.

25. The system of claim 24 , wherein the floating point arithmetic operation is selected from one of an addition operation, a subtraction operation, or an add-reduce operation.

26. The system of claim 24 , wherein the logic engine is further configured to determine whether the output result of the floating point arithmetic operation generates a floating point hardware exception.

27. The system of claim 26 , wherein the convertor engine is further configured to set a value of the output result to zero if a value of the output result is a denormal number.

28. The system of claim 26 , wherein the convertor engine is further configured to set a value of the output result to a maximum supported number if a value of the output result is a positive infinity, and wherein th

Assignees

• Marvell Asia Pte Ltd Registration No 199702379M
• Marvell Asia Pte Ltd

Inventors

• Chen Chia-Hsin
• Sodani Avinash
• Hanebutte Ulf
• Tan Rishan
• Gollamudi Soumya

Classifications

• G06F9/3861

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title

• G06F9/30181

  Instruction operation extension or modification · CPC title

• G06F9/3001 Primary

  Arithmetic instructions · CPC title

• G06F7/57

  Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations {(G06F7/49, G06F7/491 take precedence)} · CPC title

• G06F7/483 Primary

  Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} · CPC title