Printed circuit board performance evaluation techniques

Patent metadata

Field	Value
Publication number	US-11300605-B2
Application number	US-201815986521-A
Country	US
Kind code	B2
Filing date	May 22, 2018
Priority date	May 22, 2018
Publication date	Apr 12, 2022
Grant date	Apr 12, 2022

Abstract

The present disclosure describes printed circuit board performance evaluation techniques. In some cases, a printed circuit board performance evaluation process may include determining a first set of electrical properties associated with an interface between components of a printed circuit board, where the interface is disposed on an internal or external layer of the printed circuit board. After selective application of a sheet of dielectric material to a portion of a transmission line in the interface, a second set of electrical properties associated with the interface may be determined. The first set of electrical properties may be compared to the second set of electrical properties to evaluate printed circuit board performance. In other cases, the interface may include a trace inductor, and electrical properties of the interface before and after application of a ferrous material may be compared to evaluate printed circuit board performance.

First claim

What is claimed is:

1. A process of printed circuit board performance evaluation, the process comprising:
determining a first set of electrical properties associated with an interface between a first component of a printed circuit board (PCB) and a second component of the PCB, wherein the interface and the first and second components are disposed on a single external layer of the PCB;
applying a sheet of dielectric material to the external layer of the PCB, wherein the sheet of dielectric material is applied to, and overlies, a portion of a microstrip trace in the interface;
determining a second set of electrical properties associated with the interface after application of the sheet of dielectric material; and
comparing the first set of electrical properties to the second set of electrical properties to evaluate printed circuit board performance.

2. The process of claim 1 , wherein the interface includes a high-speed serial interface.

3. The process of claim 1 , wherein the interface includes a memory interface.

4. The process of claim 1 , wherein the sheet of dielectric material has a size and a permittivity selected to emulate a particular set of PCB manufacturing process parameters within a range of PCB manufacturing process parameters.

5. The process of claim 1 , wherein the external layer includes a solder mask that overlies the interface.

6. The process of claim 1 , wherein the microstrip trace connects between the first component and the second component.

7. The process of claim 1 , wherein the sheet of dielectric material includes a polytetrafluoroethylene (PTFE) sheet, a graphite sheet, a silicone sheet, a sapphire sheet, or a polyimide sheet.

Assignees

• IBM

Inventors

• Berge Layne A
• Doyle Matthew S
• Orozco Manuel
• Dangler John R
• Liang Thomas W
• Bjorgaard Jason J

Classifications

• G01R31/2813

  Checking the presence, location, orientation or value, e.g. resistance, of components or conductors (orientation of the DUT with respect to the test fixture G01R1/06705) · CPC title

• H05K1/0268

  for electrical inspection or testing · CPC title

• H05K3/0005

  for designing circuits by computer · CPC title

• H05K1/024

  Dielectric details, e.g. changing the dielectric material around a transmission line · CPC title

• H05K1/181

  associated with surface mounted components · CPC title