Receiving device, receiving method, and receiving system

Patent metadata

Field	Value
Publication number	US-11296741-B2
Application number	US-202017021384-A
Country	US
Kind code	B2
Filing date	Sep 15, 2020
Priority date	Mar 29, 2018
Publication date	Apr 5, 2022
Grant date	Apr 5, 2022

Abstract

A receiving device includes: a frequency mixer that converts a frequency of a reception signal to a baseband; an envelope demodulator; an upper sideband demodulator; and a lower sideband demodulator. Each of the envelope demodulator, the upper sideband demodulator and the lower sideband demodulator demodulates an output from the frequency mixer. The receiving device further includes: a first adder that adds an output from the envelope demodulator and an inverted output obtained by inverting an output from the upper sideband demodulator; a second adder that adds the output from the envelope demodulator and an inverted output obtained by inverting an output from the lower sideband demodulator; and a third adder that adds the output from the envelope demodulator, an inverted output obtained by inverting an output from the first adder, and an inverted output obtained by inverting an output from the second adder, to output a demodulation signal.

First claim

The invention claimed is:

1. A receiving device comprising:
a frequency mixer configured to mix a reception signal input thereto and a local signal generated by a local oscillator to convert a frequency of the reception signal to a baseband;
an envelope demodulator configured to perform envelope demodulation of an output from the frequency mixer;
an upper sideband demodulator configured to demodulate only an upper sideband of the output from the frequency mixer by single sideband demodulation;
a lower sideband demodulator configured to demodulate only a lower sideband of the output from the frequency mixer by the single sideband demodulation;
a first adder configured to add an output from the envelope demodulator and a first inverted output obtained by inverting an output from the upper sideband demodulator;
a second adder configured to add the output from the envelope demodulator and a first inverted output obtained by inverting an output from the lower sideband demodulator; and
a third adder configured to add the output from the envelope demodulator, a third inverted output obtained by inverting an output from the first adder, and a fourth inverted output obtained by inverting an output from the second adder, to output a demodulation signal.

2. The receiving device according to claim 1 ,
wherein the upper sideband demodulator comprises a first 90-degree phase shifter configured to shift, by 90 degrees, a phase of a signal obtained by multiplying the output from the frequency mixer by a synchronization signal synchronized with a carrier wave, and
wherein the lower sideband demodulator comprises a second 90-degree phase shifter configured to shift, by 90 degrees in a direction opposite to that of the first phase shifter, the phase of the signal obtained by multiplying the output from the frequency mixer by the synchronization signal.

3. The receiving device according to claim 1 , further comprising:
a first inverting circuit configured to invert the output from the upper sideband demodulator to generate the first inverted output;
a second inverting circuit configured to invert the output from the lower sideband demodulator to generate the second inverted output;
a third inverting circuit configured to invert the output from the first adder to generate the third inverted output; and
a fourth inverting circuit configured to invert the output from the second adder to generate the fourth inverted output.

4. The receiving device according to claim 3 ,
wherein each of the first inverting circuit, the second inverting circuit, the third inverting circuit and the fourth inverting circuit comprises a phase inverter configured to invert polarity of an input signal by inverting a phase of the input signal.

5. The receiving device according to claim 1 , comprising:
a processor; and
a memory storing a program,
wherein the program, when executed by the processor, causes the processor to execute at least part of processing performed by the frequency mixer, the envelope demodulator, the upper sideband demodulator, the lower sideband demodulator, the first adder, the second adder and the third adder.

6. The receiving device according to claim 1 ,
wherein the receiving device is mounted on a vehicle.

7. A receiving system comprising:
a reception signal input circuit configured to input a reception signal of a radio wave;
a demodulation processor configured to perform demodulation processing of the reception signal; and
a sound signal output circuit configured to sound-output a demodulation signal,
wherein the reception signal input circuit comprises an antenna configured to receive a radio wave of a desired wave and an input signal amplifier configured to amplify a received signal,
wherein the sound signal output circuit comprises an output signal amplifier configured to amplify the demodulation signal, and a sound output device configured to output an amplified signal as a sound signal, and
wherein the demodulation processor comprises:
a frequency mixer configured to mix the reception signal input from the reception signal input circuit and a local signal generated by a local oscillator to convert a frequency of the reception signal to a baseband;
an envelope demodulator configured to perform envelope demodulation of an output from the frequency mixer;
an upper sideband demodulator configured to demodulate only an upper sideband of the output from the frequency mixer by single sideband demodulation;
a lower sideband demodulator configured to demodulate only a lower sideband of the output from the frequency mixer by the single sideband demodulation;
a first adder configured to add an output from the envelope demodulator and a first inverted output obtained by inverting an output from the upper sideband demodulator;
a second adder configured to add the output from the envelope demodulator and a second inverted output obtained by inverting an output from the lower sideband demodulator; and
a third adder configured to add the output from the envelope demodulator, a third inverted output obtained by inverting an output from the first adder, and a fourth inverted output obtained by inverting an output from the second adder, to output the demodulation signal.

8. The receiving system according to claim 7 ,
wherein the upper sideband demodulator comprises a first 90-degree phase shifter configured to shift, by 90 degrees, a phase of a signal obtained by multiplying the output from the frequency mixer by a synchronization signal synchronized with a carrier wave, and
wherein the lower sideband demodulator comprises a second 90-degree phase shifter configured to shift, by 90 degrees in a direction opposite to that of the first phase shifter, the phase of the signal obtained by multiplying the output from the frequency mixer by the synchronization signal.

9. The receiving system according to claim 7 ,
wherein the demodulation processer further comprises:
a first inverting circuit configured to invert the output from the upper sideband demodulator to generate the first inverted output;
a second inverting circuit configured to invert the output from the lower sideband demodulator to generate the second inverted output;
a third inverting circuit configured to invert the output from the first adder to generate the third inverted output; and
a fourth inverting circuit configured to invert the output from the second adder to generate the fourth inverted output.

10. The receiving system according to claim 9 ,
wherein each of the first inverting circuit, the second inverting circuit, the third inverting circuit and the fourth inverting circuit comprises a phase inverter configured to invert polarity of an input signal by inverting a phase of the input signal.

11. The receiving system according to claim 7 , comprising:
a processor; and
a memory storing a program,
wherein the program, when executed by the processor, causes the processor to execute at least part of processing performed by the demodulation processor.

12. The receiving system according to claim 7 ,
wherein the receiving device is mounted on a vehicle.

13. The receiving system according to claim 7 ,
wherein the reception signal input circuit further comprises an analog-to-digital converter configured to convert an output from the input signal amplifier from an analog signal to a digital signal to generate the reception signal input to the demodulation processor, and
wherein the sound signal output circuit further comprises a digital-to-analog converter configured to convert the demodulation signal output from the demodulation processor from a digital signal to an

Assignees

• Panasonic Ip Man Co Ltd

Inventors

• Asada Yohei
• Fujishima Tomoyasu
• Miyashita Wataru

Classifications

• H01Q1/32

  Adaptation for use in or on road or rail vehicles · CPC title

• H03D1/00

  Demodulation of amplitude-modulated oscillations (H03D5/00, H03D9/00, H03D11/00 take precedence) · CPC title

• H04B1/1607 Primary

  Supply circuits (converters H02M; filters therefor H02M1/14; voltage stabilisers G05F1/46) · CPC title

• H04B1/302 Primary

  for single sideband receivers (demodulator circuits H03D1/24) · CPC title

• H04B1/10

  Means associated with receiver for limiting or suppressing noise or interference · CPC title