Integrated ESD event sense detector

Patent metadata

Field	Value
Publication number	US-11296501-B2
Application number	US-202016910656-A
Country	US
Kind code	B2
Filing date	Jun 24, 2020
Priority date	Feb 9, 2017
Publication date	Apr 5, 2022
Grant date	Apr 5, 2022

Abstract

As an example, a circuit is provided. The circuit includes an ESD (electrostatic discharge) clamping circuit with a control signal controlling clamping operations of the ESD clamping circuit. The circuit further includes a counter coupled to the control signal of the ESD clamping circuit. The counter produces a set of output signals responsive to the control signal. The circuit also includes a communications interface for coupling to the set of output signals of the counter. The communications interface also couples to communications circuitry external to the circuit.

First claim

We claim:

1. A circuit, comprising:
an electrostatic discharge (ESD) clamping circuit having a control signal controlling clamping operations of the ESD clamping circuit;
an asynchronous ripple counter coupled to the control signal of the ESD clamping circuit, the counter producing a set of output signals responsive to the control signal; and
a communications interface for coupling to the set of output signals of the counter and to communications circuitry external to the circuit.

2. The circuit of claim 1 , further comprising:
a bond pad coupled to the ESD clamping circuit.

3. The circuit of claim 1 , further comprising:
a series of bond pads coupled to the ESD clamping circuit.

4. The circuit of claim 1 , wherein:
the communications interface is formed to communicate via a Controller Area Network (CAN) bus wired connection with a non-volatile memory.

5. The circuit of claim 1 , wherein:
the communications interface is formed to communicate via a wireless communication link.

6. The circuit of claim 1 , wherein:
the ESD clamping circuit is a snapback circuit.

Assignees

• Texas Instruments Inc

Inventors

• Segervall Alan Erik
• Pimentel Ross Anthony
• Seth Sumantra

Classifications

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10D89/817

  FETs in a Darlington configuration · CPC title

• H10D89/711

  using bipolar transistors as protective elements · CPC title

• H10D89/60

  Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] · CPC title