Display panel including compensation semiconductor layer disposed closer to driving semiconductor layer than scan line

Patent metadata

Field	Value
Publication number	US-11296183-B2
Application number	US-202016988764-A
Country	US
Kind code	B2
Filing date	Aug 10, 2020
Priority date	Feb 24, 2020
Publication date	Apr 5, 2022
Grant date	Apr 5, 2022

Abstract

The present disclosure provides a display panel. In order to reduce a parasitic capacitance that may occur between a data line and a semiconductor layer and a crosstalk caused by the parasitic capacitance, a display panel includes a substrate, a driving thin film transistor on the substrate, including a driving semiconductor layer and a driving gate electrode, a compensation thin film transistor on the substrate, including a compensation semiconductor layer and a compensation gate electrode, a node connection line electrically connecting the driving thin film transistor to the compensation thin film transistor, a scan line extending in a first direction on the substrate, and a gate connection line electrically connected to the scan line, which includes the compensation gate electrode, wherein the compensation semiconductor layer is closer to the driving semiconductor layer than the scan line when viewed on a plane.

First claim

What is claimed is:

1. A display panel comprising:
a substrate;
a driving thin film transistor disposed on the substrate, the driving thin film transistor including a driving semiconductor layer and a driving gate electrode;
a compensation thin film transistor disposed on the substrate, the compensation thin film transistor including a compensation semiconductor layer and a compensation gate electrode;
a node connection line electrically connecting the driving thin film transistor to the compensation thin film transistor;
a scan line extending in a first direction on the substrate; and
a gate connection line electrically connected to the scan line, the gate connection line including the compensation gate electrode,
wherein the compensation semiconductor layer is disposed closer to the driving semiconductor layer than the scan line when viewed on a plane.

2. The display panel of claim 1 , further comprising a switching thin film transistor disposed on the substrate, the switching thin film transistor including a switching semiconductor layer and a switching gate electrode,
wherein the gate connection line further includes the switching gate electrode.

3. The display panel of claim 1 , wherein a resistivity value of the scan line is less than a resistivity value of the driving gate electrode.

4. The display panel of claim 1 , further comprising an insulating layer disposed between the gate connection line and the scan line,
wherein the scan line is connected to the gate connection line via a contact hole in the insulating layer.

5. The display panel of claim 1 , wherein the gate connection line and the scan line include different materials from each other.

6. The display panel of claim 1 , wherein the gate connection line comprises:
a first portion extending in a second direction that crosses the first direction; and
a second portion extending from the first portion in the first direction.

7. The display panel of claim 6 , wherein the compensation semiconductor layer includes a first portion and a second portion which extend in different directions from each other from a bending point,
the first portion of the compensation semiconductor layer overlaps the first portion of the gate connection line, and
the second portion of the compensation semiconductor layer overlaps the second portion of the gate connection line.

8. The display panel of claim 7 , wherein the gate connection line and the compensation semiconductor layer overlapping each other make a square closed loop when viewed on a plane.

9. The display panel of claim 1 , wherein the node connection line extends in the second direction crossing the first direction, and crosses the second portion of the gate connection line.

10. The display panel of claim 1 , wherein the driving semiconductor layer is curved.

11. A display panel comprising:
a scan line extending in a first direction;
a data line extending in a second direction that crosses the first direction;
a switching thin film transistor electrically connected to the scan line and the data line, the switching thin film transistor including a switching semiconductor layer and a switching gate electrode;
a driving thin film transistor electrically connected to the switching thin film transistor, the driving thin film transistor including a driving semiconductor layer and a driving gate electrode;
a compensation thin film transistor including a compensation semiconductor layer and a compensation gate electrode that are arranged with respect to a first gate insulating layer therebetween; and
a gate connection line electrically connected to the scan line, the gate connection line including the compensation gate electrode,
wherein the compensation semiconductor layer comprises:
a first portion extending in the first direction, and a second portion bent from the first portion and extending in the second direction away from the driving thin film transistor.

12. The display panel of claim 11 , wherein the compensation semiconductor layer is closer to the driving semiconductor layer than the scan line when viewed on a plane.

13. The display panel of claim 11 , wherein the gate connection line further includes a first portion extending in the second direction and a second portion extending in the first direction,
the first portion of the gate connection line overlaps the first portion of the compensation semiconductor layer, and
the second portion of the gate connection line overlaps the second portion of the compensation semiconductor layer.

14. The display panel of claim 11 , wherein the gate connection line further includes the switching gate electrode.

15. The display panel of claim 11 , further comprising a second gate insulating layer and an interlayer insulating layer disposed between the gate connection line and the scan line, and
the scan line is connected to the gate connection line via a first contact hole penetrating through the interlayer insulating layer and the second gate insulating layer.

16. The display panel of claim 11 , wherein the gate connection line includes a material different from a material in the scan line.

17. The display panel of claim 11 , further comprising:
a second gate insulating layer and an interlayer insulating layer disposed between the gate connection line and the scan line; and
a node connection line electrically connecting the driving thin film transistor to the compensation thin film transistor,
wherein one end portion of the node connection line is connected to the driving gate electrode via a second contact hole penetrating through the interlayer insulating layer and the second gate insulating layer, and
the other end portion of the node connection line is connected to the compensation semiconductor layer via a third contact hole penetrating through the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer.

18. The display device of claim 17 , wherein the node connection line extends in the second direction and crosses the second portion of the gate connection line.

19. The display device of claim 17 , wherein the node connection line includes a same material as the scan line.

20. The display panel of claim 11 , further comprising:
an emission control thin film transistor electrically connected to the driving thin film transistor, the emission control thin film transistor including an emission control semiconductor layer and an emission control gate electrode; and
an organic light-emitting diode electrically connected to the emission control thin film transistor.

Assignees

• Samsung Display Co Ltd

Inventors

• Lee Soyoung
• Kang Chulkyu
• Kim Sunghwan
• Bang Hyunchol
• Oh Soohee
• Lee Dongsun

Classifications

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/443

  adapted for preventing breakage, peeling or short circuiting · CPC title

• H10D86/423 Primary

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10K59/1216

  the pixel elements being capacitors · CPC title

• H10K59/123 Primary

  Connection of the pixel electrodes to the thin film transistors [TFT] · CPC title