Semiconductor device and method of forming the same

Patent metadata

Field	Value
Publication number	US-11296116-B2
Application number	US-201916727673-A
Country	US
Kind code	B2
Filing date	Dec 26, 2019
Priority date	Dec 26, 2019
Publication date	Apr 5, 2022
Grant date	Apr 5, 2022

Abstract

A semiconductor device includes an inter-metal dielectric layer, a first conductive line, and a first ferroelectric random access memory (FRAM) structure. The first conductive line is embedded in the inter-metal dielectric layer and extends along a first direction. The first FRAM structure is over inter-metal dielectric layer and includes a bottom electrode layer, a ferroelectric layer, and a top electrode layer. The bottom electrode layer is over the first conductive line and has an U-shaped when viewed in a cross section taken along a second direction substantially perpendicular to the first direction. The ferroelectric layer is conformally formed on the bottom electrode. The top electrode layer is over the ferroelectric layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
an inter-metal dielectric layer;
a first conductive line embedded in the inter-metal dielectric layer and extending along a first direction;
a second conductive line embedded in the inter-metal dielectric layer and extending along the first direction; and
a dielectric layer extending along a top surface of the inter-metal dielectric layer;
a first ferroelectric random access memory (FRAM) structure over the inter-metal dielectric layer, embedded in the dielectric layer, and comprising:
a bottom electrode layer over the first conductive line, having an U-shaped when viewed in a cross section taken along a second direction substantially perpendicular to the first direction, and a vertical portion of the bottom electrode layer extending upwardly from the first conductive line to beyond a top surface of the dielectric layer;
a ferroelectric layer conformally formed on the bottom electrode layer and extends across the second conductive line, the ferroelectric layer formed on the dielectric layer being in a position lower than a top end of the vertical portion of the bottom electrode layer; and

a top electrode layer over the ferroelectric layer.

2. The semiconductor device of claim 1 , wherein an area of an interface between the bottom electrode layer and the ferroelectric layer is greater than an area of an interface between the bottom electrode layer and the first conductive line.

3. The semiconductor device of claim 1 , wherein a width of the bottom electrode layer is narrower than a width of the first conductive line viewed in a cross section taken along the second direction.

4. The semiconductor device of claim 1 , wherein the ferroelectric layer has a portion directly above the bottom electrode layer and having an U-shaped when viewed in a cross section taken along the second direction.

5. The semiconductor device of claim 1 , wherein the ferroelectric layer extends vertically from a bottom portion of the bottom electrode layer and laterally beyond the vertical portion of the bottom electrode layer.

6. The semiconductor device of claim 1 , wherein the ferroelectric layer extends along the top surface of the dielectric layer.

7. The semiconductor device of claim 1 , wherein the top electrode layer extends across the second conductive line.

8. The semiconductor device of claim 1 , further comprising:
a second FRAM structure over the inter-metal dielectric layer and in contact with the first conductive line.

9. A semiconductor device, comprising:
an inter-metal dielectric layer;
a first conductive line embedded in the inter-metal dielectric layer;
a dielectric layer over the inter-metal dielectric layer;
a bottom electrode layer over the first conductive line and having a first protrusion extending above the dielectric layer and terminating prior to overlapping the dielectric layer;
a ferroelectric layer wrapping around three sides of the first protrusion of the bottom electrode layer; and
a top electrode layer over the ferroelectric layer.

10. The semiconductor device of claim 9 , wherein the bottom electrode layer has a second protrusion protruding above the dielectric layer, the ferroelectric layer wrapping around three sides of the second protrusion.

11. The semiconductor device of claim 9 , wherein an area of an interface between the ferroelectric layer and the top electrode layer is greater than an area of an interface between the bottom electrode layer and the first conductive line.

12. The semiconductor device of claim 9 , wherein the top electrode layer wraps around the three sides of the first protrusion.

13. The semiconductor device of claim 9 , wherein the dielectric layer overlaps a portion of the first conductive line and non-overlaps the bottom electrode layer.

14. The semiconductor device of claim 9 , wherein the bottom electrode layer has a U-shape when viewed in a cross section.

15. The semiconductor device of claim 9 , wherein the ferroelectric layer is further formed on the dielectric layer.

16. The semiconductor device of claim 9 , further comprising:
a second conductive line embedded in the inter-metal dielectric layer, the ferroelectric layer extending across the second conductive line.

17. The semiconductor device of claim 9 , further comprising:
a second conductive line embedded in the inter-metal dielectric layer, the top electrode layer extending across the second conductive line.

18. A semiconductor device, comprising:
a first dielectric layer;
a conductive line embedded in the first dielectric layer;
a second dielectric layer over the first dielectric layer and the conductive line;
a bottom electrode layer partially embedded in the second dielectric layer and having a vertical portion extending upwardly from the conductive line to beyond a top surface of the second dielectric layer;
a ferroelectric layer conformally formed on the bottom electrode layer and the second dielectric layer, the ferroelectric layer formed on the second dielectric layer being in a position lower than a top end of the vertical portion of the bottom electrode layer; and
a top electrode layer conformally formed on the ferroelectric layer.

19. The semiconductor device of claim 18 , wherein the bottom electrode layer has a U-shape when viewed in a cross section taken along a lengthwise direction of the conductive line.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Fu-Chen
• Tu Kuo-Chi
• Chen Tzu-Yu
• Shih Sheng-Hung

Classifications

• H10D1/692

  Electrodes · CPC title

• H10D1/688 Primary

  comprising barrier layers to prevent diffusion of hydrogen or oxygen · CPC title

• H10D1/716

  having vertical extensions · CPC title

• G11C11/223

  using MOS with ferroelectric gate insulating film · CPC title

• G11C11/221

  using ferroelectric capacitors · CPC title