Memory modules and stacked memory devices

Patent metadata

Field	Value
Publication number	US-11295805-B2
Application number	US-202017095008-A
Country	US
Kind code	B2
Filing date	Nov 11, 2020
Priority date	Apr 20, 2020
Publication date	Apr 5, 2022
Grant date	Apr 5, 2022

Abstract

A memory module includes semiconductor memory devices mounted on a circuit board and a control device mounted on the circuit board. Each semiconductor memory device includes a memory cell array to store data. The control device receives a command and an access address from an external device and provides the command and the access address to the semiconductor memory devices. Each semiconductor memory device performs an address swapping operation to randomly swap a portion of bits of the access address to generate a swapped address in response to a power-up signal or a reset signal, and enables a respective target word-line from among word-lines in the memory cell array such that two or more of the semiconductor memory devices enable different target word-lines in response to the access address.

First claim

What is claimed is:

1. A memory module comprising:
a plurality of semiconductor memory devices mounted on a circuit board, each of plurality of semiconductor memory devices including a memory cell array to store data; and
a control device mounted on the circuit board, and configured to receive a command and an access address from an external device and to provide the command and the access address to the plurality of semiconductor memory devices,
wherein each of the plurality of semiconductor memory devices is configured to perform an address swapping operation to randomly swap a portion of bits of the access address to generate a swapped address in response to a power-up signal or a reset signal, and to enable a respective target word-line from among a plurality of word-lines in the memory cell array of the semiconductor memory device such that at least two of the plurality of semiconductor memory devices enable different target word-lines in response to the access address.

2. The memory module of claim 1 , wherein:
each of the plurality of semiconductor memory devices includes an address swapping circuit configured to perform the address swapping operation on a row address in the access address.

3. The memory module of claim 2 , wherein the address swapping circuit includes:
a random selection signal generator configured to randomly generate random selection signals in response to the power-up signal or the reset signal; and
an address swapper configured to swap a portion of bits of the row address to generate the swapped address, and output the swapped address in response to the random selection signals.

4. The memory module of claim 3 ,
wherein the random selection signal generator includes a physically unclonable function (PUF) configured to generate the random selection signals in response to the power-up signal or the reset signal.

5. The memory module of claim 3 ,
wherein the random selection signal generator includes an anti-fuse circuit in which the random selection signals are randomly programmed, the anti-fuse circuit configured to output the random selection signals in response to the power-up signal or the reset signal, and
wherein the random selection signals are programmed in the anti-fuse circuits in the plurality of semiconductor memory devices in different sequences.

6. The memory module of claim 3 ,
wherein the address swapper includes a plurality of multiplexers configured to select different bits of the portion of bits of the row address to generate the swapped address, and to output the swapped address in response to combination of the random selection signals.

7. The memory module of claim 1 , wherein each of the plurality of semiconductor memory devices further includes:
a row decoder, coupled to the memory cell array through the plurality of word-lines, the row decoder configured to receive the swapped address; and
a power-up signal generator configured to generate the power-up signal in response to a power supply voltage being equal to or greater than a reference voltage.

8. The memory module of claim 7 , wherein each of the plurality of semiconductor memory devices further includes:
an address register configured to receive the access address and the power-up signal, and the address register includes an address swapping circuit that performs the address swapping operation.

9. The memory module of claim 7 , wherein the row decoder is configured to enable one of the plurality of word-lines as the target word-line, in response to the swapped address.

10. The memory module of claim 1 , wherein the plurality of semiconductor memory devices are configured to distribute victim word-lines disturbed by the access address in response to the access address being accessed more frequently than a reference number of access times.

11. A memory module comprising:
a plurality of semiconductor memory devices mounted on a circuit board, each of plurality of semiconductor memory devices including a memory cell array to store data; and
a control device mounted on the circuit board, and configured to receive a command and an access address from an external device, perform an address swapping operation to randomly swap a portion of bits of the access address to generate swapped addresses in response to a power-up signal or a reset signal and provide the command and the swapped addresses to the plurality of semiconductor memory devices,
wherein the plurality of semiconductor memory devices are configured to enable respective target word-lines among from a plurality of word-lines in the memory cell arrays such that at least two of the plurality of semiconductor memory devices enable different target word-lines with respect to the access address.

12. The memory module of claim 11 , wherein the control device includes:
a power-up signal generator configured to generate the power-up signal in response to a power supply voltage provided to the control device being equal to or greater than a reference voltage; and
a plurality of address swapping circuits corresponding respectively to the plurality of semiconductor memory devices, the plurality of address swapping circuits configured to receive the power-up signal and perform the address swapping operation on a row address in the access address.

13. The memory module of claim 12 , wherein each of the plurality of address swapping circuits includes:
a random selection signal generator configured to randomly generate random selection signals in response to the power-up signal or the reset signal; and
an address swapper configured to swap a portion of bits of the row address to generate a swapped address and output the swapped address in response to the random selection signals.

14. The memory module of claim 13 ,
wherein the random selection signal generator includes a physically unclonable function (PUF) configured to generate the random selection signals in response to the power-up signal or the reset signal.

15. The memory module of claim 13 ,
wherein the random selection signal generator includes an anti-fuse circuit in which the random selection signals are randomly programmed, the anti-fuse circuit configured to output the random selection signals in response to the power-up signal or the reset signal, and
wherein the random selection signals are programmed in the anti-fuse circuits.

16. The memory module of claim 13 ,
wherein the address swapper includes a plurality of multiplexers configured to select different bits of the portion of bits of the row address to generate the swapped address and output the swapped address in response to combination of the random selection signals.

17. The memory module of claim 13 , wherein,
each of the plurality of semiconductor memory devices further includes a row decoder, coupled to the memory cell array through the plurality of word-lines, the row decoder configured to receive the swapped address, and
the row decoder is configured to enable one of the plurality of word-lines as the target word-line, in response to the swapped address.

18. A stacked memory device comprising:
a buffer die configured to receive a command and an access address from an external device,
a plurality of memory dies stacked on the buffer die, each of the plurality of memory dies including a memory cell array to store data; and
a plurality of through silicon vias (TSVs) extending through the plurality of memory dies to connect to the buffer die,
wherein each of the plurality of memory dies is configured to receive the access address through the TSVs, p

Assignees

• Samsung Electronics Co Ltd

Inventors

• O Seongil
• Son Jongpil
• Kwon Sanghyuk

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• G11C11/4087 Primary

  Address decoders, e.g. bit - or word line decoders; Multiple line decoders · CPC title