Loop delay compensation in a sigma-delta modulator

Patent metadata

Field	Value
Publication number	US-11290123-B2
Application number	US-202117183433-A
Country	US
Kind code	B2
Filing date	Feb 24, 2021
Priority date	May 27, 2020
Publication date	Mar 29, 2022
Grant date	Mar 29, 2022

Abstract

A circuit includes a transconductance stage having first and second outputs. The circuit also includes a comparator having first and second inputs. The first input is coupled to the first output, and the second input is coupled to the second output. The comparator includes first through fifth transistors and a pair of cross-coupled transistors. The pair of cross-coupled transistors is coupled to the second current terminals of the first and second transistors. The second current terminal of the third transistor is coupled to the second current terminal of the first transistor, and the first current terminals of the first, second, and third transistors are coupled together. The second current terminals of the fourth and fifth transistors are coupled together and to the control input of the third transistor.

First claim

What is claimed is:

1. A circuit, comprising:
a transconductance stage having first and second outputs;
a comparator having first and second inputs, the first input coupled to the first output, and the second input coupled to the second output, the comparator including:
a first transistor having a control input and first and second current terminals;
a second transistor having a control input and first and second current terminals;
a third transistor having a control input and first and second current terminals, the second current terminal of the third transistor is coupled to the second current terminal of the first transistor, and the first current terminals of the first, second, and third transistors are coupled together;
a fourth transistor having a control input and first and second current terminals; and
a fifth transistor having a control input and first and second current terminals, the second current terminals of the fourth and fifth transistors are coupled together and to the control input of the third transistor.

2. The circuit of claim 1 , wherein the control of the first transistor comprises the first input of the comparator, and the control input of the second transistor comprises the second input of the comparator.

3. The circuit of claim 1 , wherein:
the comparator has first and second comparator outputs;
the control input of the fifth transistor is coupled to the first comparator output; and
the control input of the fourth transistor is coupled to the second comparator output.

4. The circuit of claim 3 , wherein:
the first current terminal of the fourth transistor is coupled to a first reference voltage node; and
the first current terminal of the fifth transistor is coupled to a second reference voltage node.

5. The circuit of claim 4 , wherein the first reference voltage node is configured to have a larger voltage than a voltage on the second reference voltage node.

6. The circuit of claim 1 , wherein:
the first current terminal of the fourth transistor is coupled to a first reference voltage node; and
the first current terminal of the fifth transistor is coupled to a second reference voltage node.

7. The circuit of claim 1 , wherein:
a sixth transistor having a control input and first and second current terminals, the second current terminal of the sixth transistor is coupled to the second current terminal of the second transistor;
a seventh transistor having a control input and first and second current terminals; and
an eighth transistor having a control input and first and second current terminals, the second current terminals of the seventh and eighth transistors are coupled together and to the control input of the sixth transistor.

8. The circuit of claim 7 , wherein:
the comparator has first and second comparator outputs;
the control inputs of the fifth and seventh transistors are coupled to the first comparator output; and
the control inputs of the fourth and eighth transistors are coupled to the second comparator output.

9. The circuit of claim 8 , wherein:
the first current terminals of the fourth and seventh transistors are coupled to a first reference voltage node; and
the first current terminals of the fifth and eighth transistor are coupled to a second reference voltage.

10. The circuit of claim 1 , further comprising:
a first dither circuit coupled to the first transistor; and
a second dither circuit coupled to the second transistor.

11. A circuit, comprising:
a comparator having a front-end and a back-end, the comparator's back-end having a first comparator output and a second comparator output, comparator's front-end including:
a first transistor having a control input and first and second current terminals, the control input of the first transistor is coupled to the first comparator output;
a second transistor having a control input and first and second current terminals, the control input of the second transistor is coupled to the second comparator output;
a third transistor having a control input and first and second current terminals, the second current terminal of the third transistor is coupled to the second current terminal of the first transistor, and the first current terminals of the first, second, and third transistors are coupled together;
a fourth transistor having a control input and first and second current terminals; and
a fifth transistor having a control input and first and second current terminals, the second current terminals of the fourth and fifth transistors are coupled together and to the control input of the third transistor.

12. The circuit of claim 11 , wherein:
the control input of the fifth transistor is coupled to the first comparator output; and
the control input of the fourth transistor is coupled to the second comparator output.

13. The circuit of claim 11 , wherein:
the first current terminal of the fourth transistor is coupled to a first reference voltage node; and
the first current terminal of the fifth transistor is coupled to a second reference voltage node.

14. The circuit of claim 11 , further comprising:
a sixth transistor having a control input and first and second current terminals, the second current terminal of the sixth transistor is coupled to the second current terminal of the second transistor;
a seventh transistor having a control input and first and second current terminals; and
an eighth transistor having a control input and first and second current terminals, the second current terminals of the seventh and eighth transistors are coupled together and to the control input of the sixth transistor.

Assignees

• Texas Instruments Inc

Inventors

• Agrawal Meghna

Classifications

• H03M3/438

  the modulator having a higher order loop filter in the feedforward path · CPC title

• H03K5/249 Primary

  using clock signals · CPC title

• H03M3/458

  Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title

• H03M1/06

  Continuously compensating for, or preventing, undesired influence of physical parameters (periodically, {e.g. by using stored correction values,} H03M1/10) · CPC title

• H03K5/2481

  with at least one differential stage · CPC title