Frequency synthesizer

Patent metadata

Field	Value
Publication number	US-11290118-B2
Application number	US-202017128791-A
Country	US
Kind code	B2
Filing date	Dec 21, 2020
Priority date	Jun 11, 2020
Publication date	Mar 29, 2022
Grant date	Mar 29, 2022

Abstract

A frequency synthesizer includes a phase-locked loop (PLL). The PLL includes a first voltage-controlled oscillator (VCO) and a second VCO, each comprising an oscillator, a capacitor bank, and a bias circuit. The capacitor bank is configured to selectably adjust an output frequency of the oscillator. The bias circuit is configured to provide a bias current to the oscillator, and includes a current digital-to-analog converter (IDAC), and an amplifier coupled to the IDAC and configured to drive the oscillator.

First claim

What is claimed is:

1. A frequency synthesizer, comprising:
a phase-locked loop (PLL) comprising:
an oscillator control circuit comprising a capacitor control terminal and a current control terminal;
a voltage-controlled oscillator (VCO) circuit comprising:
an oscillator comprising a capacitor terminal and a bias current terminal;
a capacitor bank comprising
an oscillator terminal coupled to the capacitor terminal; and
a selection terminal coupled to the capacitor control terminal;

a bias circuit comprising:
a current digital-to-analog converter (IDAC) comprising:
 an input terminal coupled to the current control terminal; and
 an output terminal;
a filter capacitor terminal;
a bias current terminal; and
an amplifier comprising:
 an input terminal coupled to the output terminal of the IDAC; and
 an output terminal coupled to the filter capacitor terminal and the bias current terminal.

2. The frequency synthesizer of claim 1 , wherein:
the VCO comprises an output terminal; and
the PLL further comprises:
a mute terminal;
an output buffer circuit comprising:
an enable terminal coupled to the mute terminal; and
an input terminal coupled to the output terminal of the VCO.

3. The frequency synthesizer of claim 1 , wherein:
the VCO is a first VCO; and
the PLL comprises:
a second VCO;
a calibration look-up table; and
a calibration circuit configured to:
for each of a plurality of frequencies:
determine which of the first VCO or the second VCO to use to generate a selected frequency; and
store an identifier of the first VCO or the second VCO at a location of the calibration look-up table associated with the selected frequency.

4. The frequency synthesizer of claim 3 , wherein the calibration circuit is configured to:
select, for the selected frequency, a capacitor of the capacitor bank to use to generate the selected frequency; and
store an identifier of the capacitor at the location of the calibration look-up table associated with the selected frequency.

5. The frequency synthesizer of claim 3 , wherein the calibration circuit is configured to:
select, for the selected frequency, a bias current to use to generate the selected frequency; and
store an identifier of the bias current at the location of the calibration look-up table associated with the selected frequency.

6. The frequency synthesizer of claim 3 , wherein:
the PLL further comprises:
a first frequency doubler circuit coupled to the VCO circuit; and
a second frequency doubler circuit coupled to the VCO circuit; and
the calibration circuit is configured to:
select, for the selected frequency, the first frequency doubler circuit or the second frequency doubler circuit to use to generate the selected frequency; and
store an identifier of the first frequency doubler circuit or the second frequency doubler circuit at the location of the calibration look-up table associated with the selected frequency.

7. The frequency synthesizer of claim 3 , wherein the oscillator control circuit is configured to apply information stored at the location of the calibration look-up table to set the PLL to generate the selected frequency.

8. The frequency synthesizer of claim 1 , wherein:
the PLL is a first PLL; and
the frequency synthesizer comprises:
a second PLL; and
a synthesizer control circuit coupled to the first PLL and the second PLL, and configured to change an output frequency of the frequency synthesizer by enabling the second PLL and disabling the first PLL.

9. A frequency synthesizer, comprising:
a phase-locked loop (PLL), comprising:
a first voltage-controlled oscillator (VCO) and a second VCO, each comprising:
an oscillator;
a capacitor bank configured to selectably adjust an output frequency of the oscillator; and
a bias circuit configured to provide a bias current to the oscillator, and comprising:
a current digital-to-analog converter (IDAC); and

an amplifier coupled to the IDAC and configured to drive the oscillator;

wherein:
the PLL comprises:
a calibration look-up table; and
a calibration circuit configured to:
initialize the calibration look-up table for a plurality of frequencies;
and
for each frequency of the plurality of frequencies:
determine which of the first VCO or the second VCO to use to generate the frequency; and
store an identifier of the first VCO or the second VCO at a location of the calibration look-up table associated with the frequency.

10. The frequency synthesizer of claim 9 , wherein the calibration circuit is configured to:
select, for the frequency, a capacitor of the capacitor bank to use to generate the frequency; and
store an identifier of the capacitor at the location of the calibration look-up table associated with the frequency.

11. The frequency synthesizer of claim 9 , wherein the calibration circuit is configured to:
select, for the frequency, a bias current to use to generate the frequency; and
store an identifier of the bias current at the location of the calibration look-up table associated with the frequency.

12. The frequency synthesizer of claim 9 , wherein:
the PLL further comprises:
a first frequency doubler circuit configured to double the output frequency of the oscillator; and
a second frequency doubler circuit configured to double the output frequency of the oscillator; and

the calibration circuit is configured to:
select, for the frequency, the first frequency doubler circuit or the second frequency doubler circuit to use to generate the frequency; and
store an identifier of the first frequency doubler circuit or the second frequency doubler circuit at the location of the calibration look-up table associated with the frequency.

13. The frequency synthesizer of claim 9 , further comprising an oscillator control circuit is configured to apply information stored at the location of the calibration look-up table to set the PLL to generate a selected frequency.

14. A frequency synthesizer, comprising:
a first phase-locked loop (PLL) and a second PLL, each comprising:
a first voltage-controlled oscillator (VCO) and a second VCO, each comprising:
an oscillator;
a capacitor bank configured to selectably adjust an output frequency of the oscillator; and
a bias circuit configured to provide a bias current to the oscillator, and comprising:
a current digital-to-analog converter (IDAC); and
an amplifier coupled to the IDAC and configured to drive the oscillator;

a calibration look-up table configured to store a VCO selection, a capacitor selection, and bias current selection for each of multiple frequencies; and
a calibration circuit configured to initialize the calibration look-up table; and

an oscillator control circuit configured to apply the VCO selection, the capacitor selection, and the bias current selection stored in the calibration look-up table for a given frequency to set the oscillator to produce the given frequency;
wherein the calibration circuit is configured to:

for the given frequency of the multiple frequencies:
determine which of the first VCO or the second VCO to use to generate the given frequency; and
store an identifier of the first VCO or the second VCO at a location of the calibration look-up table associated with the given frequency.

15. The frequency synthesizer of claim 14 , wherein the calibration circuit is configured to:
select, for the given frequency, a capacitor of the capacitor bank to use to generate the given frequency; and
store an identifier of the capacitor at the location of the calibration look-up table associated with th

Assignees

• Texas Instruments Inc

Inventors

• Theertham Srinivas
• Chand Jagdish
• Darwhekar Yogesh
• Mukherjee Subhashish
• Janardhanan Jayawardan
• Meda Uday Kiran
• Thakkar Arpan Sureshbhai
• Bhatia Apoorva
• Kumar Pranav

Classifications

• H03L7/087 Primary

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title

• H03L7/189

  comprising a D/A converter for generating a coarse tuning voltage · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03L7/085

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title