Operational amplifier and chip

Patent metadata

Field	Value
Publication number	US-11290075-B2
Application number	US-202016938067-A
Country	US
Kind code	B2
Filing date	Jul 24, 2020
Priority date	Jan 26, 2018
Publication date	Mar 29, 2022
Grant date	Mar 29, 2022

Abstract

An operational amplifier includes a differential amplification circuit configured to receive and amplify an input voltage to generate an output voltage, and receive a feedback signal, and the feedback signal adjusts a common-mode voltage of the output voltage, a reference voltage generation circuit configured to detect status information of the operational amplifier, and generate a reference voltage based on the status information, where the status information includes a temperature or an operating voltage of the operational amplifier, and a common-mode feedback circuit configured to receive the output voltage and the reference voltage, and provide the feedback signal to the differential amplification circuit based on the output voltage and the reference voltage.

First claim

What is claimed is:

1. An operational amplifier comprising:
a differential amplification circuit configured to:
receive and amplify an input voltage to generate an output voltage;
receive a feedback signal; and
adjust a common-mode voltage of the output voltage based on the feedback signal;

a reference voltage generation circuit comprising:
a first metal-oxide-semiconductor (MOS) transistor, wherein a gate of the first MOS transistor is short-circuited to a drain of the first MOS transistor;
a first bias circuit configured to provide a drain current to the first MOS transistor; and
a first summation circuit, wherein an input terminal of the first summation circuit is configured to receive a drain voltage of the first MOS transistor and an operating voltage,
wherein the reference voltage generation circuit is configured to:
detect status information of the operational amplifier, wherein the status information comprises a temperature or an operating voltage of the operational amplifier; and
generate a reference voltage based on the status information, wherein the reference voltage is a voltage at an output terminal of the first summation circuit; and

a common-mode feedback circuit coupled to the differential amplification circuit and the reference voltage generation circuit and configured to:
receive the output voltage and the reference voltage; and
provide the feedback signal to the differential amplification circuit based on the output voltage and the reference voltage.

2. The operational amplifier of claim 1 , wherein the reference voltage generation circuit comprises a voltage divider circuit that is located between a circuit point of the operating voltage and a ground, wherein the voltage divider circuit comprises a voltage divider node, and wherein the reference voltage is a voltage of the voltage divider node.

3. The operational amplifier of claim 1 , wherein a process of the first MOS transistor is the same as that of other MOS transistors in the operational amplifier.

4. The operational amplifier of claim 1 , wherein the common-mode feedback circuit comprises:
a second summation circuit configured to:
receive the output voltage; and
generate the common-mode voltage based on the output voltage;

a first level switching circuit coupled to the second summation circuit and configured to:
receive the common-mode voltage; and
convert the common-mode voltage to obtain a first voltage;

a second level switching circuit configured to:
receive the reference voltage; and
convert the reference voltage to obtain a second voltage; and

an amplification circuit coupled to the first level switching circuit and the second level switching circuit and comprising:
input pair transistors comprising:
a second metal-oxide-semiconductor (MOS) transistor, wherein a gate of the second MOS transistor is configured to receive the first voltage, and wherein the first voltage enables the second MOS transistor to operate in a saturation region; and
a third MOS transistor, wherein a gate of the third MOS transistor is configured to receive the second voltage, and wherein the second voltage enables the third MOS transistor to operate in the saturation region; and
an output terminal configured to generate the feedback signal.

5. The operational amplifier of claim 1 , wherein the differential amplification circuit comprises K stages of amplification circuits, wherein a (K−1) th stage amplification circuit comprises a second bias circuit, wherein the second bias circuit comprises a fourth metal-oxide-semiconductor (MOS) transistor, wherein a gate of the fourth MOS transistor is configured to receive the feedback signal, and wherein k≥2.

6. The operational amplifier of claim 1 , wherein the common-mode feedback circuit further comprises a filter circuit configured to:
receive the common-mode voltage; and
filter out a direct current component of the common-mode voltage to obtain a fast path feedback signal, wherein the fast path feedback signal is an alternating current component of the common-mode voltage.

7. The operational amplifier of claim 6 , wherein the differential amplification circuit comprises K stages of amplification circuits, wherein a K th stage amplification circuit comprises a third bias circuit, wherein the third bias circuit comprises a fifth metal-oxide-semiconductor (MOS) transistor, wherein a gate of the fifth MOS transistor is configured to receive the fast path feedback signal, and wherein K≥2.

8. The operational amplifier of claim 7 , wherein the common-mode voltage is directly coupled to the K th stage amplification circuit.

9. A chip comprising:
an operational amplifier comprising:
a differential amplification circuit configured to:
receive and amplify an input voltage to generate an output voltage;
receive a feedback signal; and
adjust a common-mode voltage of the output voltage based on the feedback signal;

a reference voltage generation circuit configured to:
detect status information of the operational amplifier, wherein the status information comprises a temperature or an operating voltage of the operational amplifier; and
generate a reference voltage based on the status information; and

a common-mode feedback circuit coupled to the differential amplification circuit and the reference voltage generation circuit and configured to:
receive the output voltage and the reference voltage; and
provide the feedback signal to the differential amplification circuit based on the output voltage and the reference voltage,

wherein the common-mode feedback circuit further comprises a filter circuit configured to:
receive the common-mode voltage; and
filter out a direct current component of the common-mode voltage to obtain a fast path feedback signal, wherein the fast path feedback signal is an alternating current component of the common-mode voltage.

10. The chip of claim 9 , wherein the reference voltage generation circuit comprises:
a first metal-oxide-semiconductor (MOS) transistor, wherein a gate of the first MOS transistor is short-circuited to a drain of the first MOS transistor, and wherein the reference voltage is a drain voltage of the first MOS transistor; and
a first bias circuit configured to provide a drain current to the first MOS transistor.

11. The chip of claim 10 , wherein a process of the first MOS transistor is the same as that of other MOS transistors in the operational amplifier.

12. The chip of claim 9 , wherein the reference voltage generation circuit comprises a voltage divider circuit that is located between a circuit point of the operating voltage and a ground, wherein the voltage divider circuit comprises a voltage divider node, and wherein the reference voltage is a voltage of the voltage divider node.

13. The chip of claim 9 , wherein the reference voltage generation circuit comprises:
a first metal-oxide-semiconductor (MOS) transistor, wherein a gate of the first MOS transistor is short-circuited to a drain of the first MOS transistor;
a first bias circuit configured to provide a drain current to the first MOS transistor; and
a first summation circuit, wherein an input terminal of the first summation circuit is configured to receive a drain voltage of the first MOS transistor and the operating voltage, and wherein the reference voltage is a voltage at an output terminal of the first summation circuit.

14. The chip of claim 9 , wherein the common-mode feedback circuit comprises:
a second summation circuit configured to:
receive the output voltage; and
generate the common-mode voltage based on the output voltage;

a first level s

Assignees

• Huawei Tech Co Ltd

Inventors

• Li Haixi

Classifications

• H03F2203/45404

  the CMCL comprising capacitors containing, not in parallel with the resistors, an addition circuit · CPC title

• H03F3/68

  Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics {(power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602)} · CPC title

• H03F2203/45422

  the CMCL comprising one or more capacitors not as integrating capacitor, e.g. for stability purposes · CPC title

• H03F2200/471

  the voltage being sensed · CPC title

• H03F3/45695

  by using feedforward means (H03F3/45744 takes precedence) · CPC title