Common-mode insensitive current-sensing topology in full-bridge driver

Patent metadata

Field	Value
Publication number	US-11290071-B2
Application number	US-202017003564-A
Country	US
Kind code	B2
Filing date	Aug 26, 2020
Priority date	May 1, 2020
Publication date	Mar 29, 2022
Grant date	Mar 29, 2022

Abstract

A system may include a Class-D stage comprising a first high-side switch coupled between a supply voltage and a first output terminal of the Class-D stage, a second high-side switch coupled between the supply voltage and a second output terminal of the Class-D stage, a first low-side switch coupled between a ground voltage and the first output terminal, and a second low-side switch coupled between the ground voltage and the second output terminal. The system may also include current sensing circuitry comprising a first sense resistor coupled between the first high-side switch and the supply voltage, such that an output current through a load coupled between the first output terminal and the second output terminal causes a first sense voltage proportional to the output current across the first sense resistor when the first high-side switch is activated. The current sensing circuitry may also include a second sense resistor coupled between the second high-side switch and the supply voltage, such that an output current through the load causes a second sense voltage proportional to the output current across the second sense resistor when the second high-side switch is activated. The system may also include measurement circuitry configured to measure the first sense voltage and the second sense voltage to determine the output current.

First claim

What is claimed is:

1. A system comprising:
a Class-D stage comprising:
a first high-side switch coupled between a supply voltage and a first output terminal of the Class-D stage;
a second high-side switch coupled between the supply voltage and a second output terminal of the Class-D stage;
a first low-side switch coupled between a ground voltage and the first output terminal; and
a second low-side switch coupled between the ground voltage and the second output terminal; and
current sensing circuitry comprising:
a first sense resistor coupled between the first high-side switch and the supply voltage, such that an output current through a load coupled between the first output terminal and the second output terminal causes a first sense voltage proportional to the output current across the first sense resistor when the first high-side switch is activated;
a second sense resistor coupled between the second high-side switch and the supply voltage, such that an output current through the load causes a second sense voltage proportional to the output current across the second sense resistor when the second high-side switch is activated; and
measurement circuitry configured to measure the first sense voltage and the second sense voltage to determine the output current; and
a calibration subsystem comprising a first calibration resistor and a second calibration resistor and configured to calibrate for mismatch between common mode phases of the Class-D stage.

2. The system of claim 1 , wherein the measurement circuitry comprises an amplifier configured to amplify a difference between the first sense voltage and the second sense voltage to generate a combined sense voltage.

3. The system of claim 1 , wherein the Class-D stage further comprises:
a third sense resistor coupled between the first low-side switch and the ground voltage, such that an output current through the load causes a third sense voltage proportional to the output current across the third sense resistor when the first low-side switch is activated; and
a fourth sense resistor coupled between the second low-side switch and the ground voltage, such that an output current through the load causes a fourth sense voltage proportional to the output current across the fourth sense resistor when the second low-side switch is activated;
wherein the measurement circuitry is configured to measure the third sense voltage and the fourth sense voltage to determine the output current.

4. The system of claim 3 , wherein the measurement circuitry further comprises:
a first amplifier configured to amplify a difference between the first sense voltage and the second sense voltage to generate a high-side sense voltage; and
a second amplifier configured to amplify a difference between the third sense voltage and the fourth sense voltage to generate a low-side sense voltage.

5. The system of claim 4 , wherein the measurement circuitry further comprises a combiner configured to combine the high-side sense voltage and the low-side sense voltage to generate a combined sense voltage indicative of the output current.

6. The system of claim 1 , wherein the first calibration resistor is coupled between the first sense resistor and an amplifier and the second calibration resistor is coupled between the second sense resistor and the amplifier.

7. The system of claim 1 , wherein the first calibration resistor and the second calibration resistor comprise feedback resistors of an amplifier.

8. The system of claim 1 , wherein the calibration subsystem is further configured to:
calibrate a first variable resistance of the first calibration resistor when the second sense resistor is in a fully-differential current path of the output current; and
calibrate a second variable resistance of the second calibration resistor when the first sense resistor is in the fully-differential current path of the output current.

9. The system of claim 1 , wherein the calibration subsystem is further configured to:
calibrate a first variable resistance of the first calibration resistor when a polarity of the output current is a first polarity; and
calibrate a second variable resistance of the first calibration resistor when the polarity of the output current is a second polarity.

10. The system of claim 9 , wherein the calibration subsystem is further configured to alternate between calibration of the first variable resistance and the second variable resistance, and vice versa, at zero crossings of the output current.

11. A method, in a Class-D stage comprising a first high-side switch coupled between a supply voltage and a first output terminal of the Class-D stage, a second high-side switch coupled between the supply voltage and a second output terminal of the Class-D stage, a first low-side switch coupled between a ground voltage and the first output terminal, and a second low-side switch coupled between the ground voltage and the second output terminal, comprising:
measuring a first sense voltage with a first sense resistor coupled between the first high-side switch and the supply voltage, such that an output current through a load coupled between the first output terminal and the second output terminal causes the first sense voltage proportional to the output current across the first sense resistor when the first high-side switch is activated;
measuring a second sense voltage with a second sense resistor coupled between the second high-side switch and the supply voltage, such that an output current through the load causes the second sense voltage proportional to the output current across the second sense resistor when the second high-side switch is activated;
determining the output current based on both of the first sense voltage and the second sense voltage; and
calibrating for mismatch between common mode phases of the Class-D with a calibration subsystem comprising a first calibration resistor and a second calibration resistor and configured to calibrate for mismatch between common mode phases of the Class-D stage.

12. The method of claim 11 , further comprising amplifying a difference between the first sense voltage and the second sense voltage to generate a combined sense voltage.

13. The method of claim 11 , further comprising:
measuring a third sense voltage with a third sense resistor coupled between the first low-side switch and the ground voltage, such that an output current through the load causes the third sense voltage proportional to the output current across the third sense resistor when the first low-side switch is activated;
measuring a fourth sense voltage with a fourth sense resistor coupled between the second low-side switch and the ground voltage, such that an output current through the load causes the fourth sense voltage proportional to the output current across the third sense resistor when the second low-side switch is activated; and
determining the output current based on the first sense voltage, the second sense voltage, the third sense voltage, and the fourth sense voltage.

14. The method of claim 13 , further comprising:
amplifying a difference between the first sense voltage and the second sense voltage to generate a high-side sense voltage; and
amplifying a difference between the third sense voltage and the fourth sense voltage to generate a low-side sense voltage.

15. The method of claim 14 , further comprising combining the high-side sense voltage and the low-side sense voltage to generate a combined sense voltage indicative of the output current.

16. The method of claim 11 , wherein the first calibration resistor is coupled bet

Assignees

• Cirrus Logic Int Semiconductor Ltd
• Cirrus Logic Inc

Inventors

• Zanbaghi Ramin
• Peterson Cory J
• Ilango Anand
• Kimball Eric

Classifications

• G01R19/0092

  Measuring current only · CPC title

• G01R1/203

  Resistors used for electric measuring, e.g. decade resistors standards, resistors for comparators, series resistors, shunts (resistors in general H01C; microwave or radiowave terminations H01P1/26; coupling devices H01R) · CPC title

• H03F3/45

  Differential amplifiers (differential sense amplifiers G11C7/062) · CPC title

• H03F3/2173 Primary

  of the bridge type · CPC title

• G05F1/461 Primary

  using an operational amplifier as final control device · CPC title