Crystal oscillator interconnect architecture with noise immunity

Patent metadata

Field	Value
Publication number	US-11290059-B2
Application number	US-201916714390-A
Country	US
Kind code	B2
Filing date	Dec 13, 2019
Priority date	Nov 3, 2016
Publication date	Mar 29, 2022
Grant date	Mar 29, 2022

Abstract

An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.

First claim

We claim:

1. An apparatus comprising:
an oscillator;
a near-end capacitor coupled to a first interconnect, wherein the first interconnect is coupled to the oscillator;
a far-end capacitor coupled to a second interconnect, wherein the second interconnect is coupled to the oscillator;
a resistor directly conductively coupled to the first and second interconnects to provide a feedback path, wherein the resistor is closer to the near-end capacitor than the far-end capacitor;
an inverting amplifier coupled to the first and second interconnects; and
a signal conditioning circuitry coupled to the inverting amplifier, wherein the signal conditioning circuitry comprises:
a high pass filter;
a pair of AC coupling capacitors coupled to the high pass filter;
a low pass filter coupled to the pair of AC coupling capacitors; and
an analog to digital converter (ADC) coupled to the low pass filter.

2. The apparatus of claim 1 , wherein the oscillator comprises a crystal.

3. The apparatus of claim 1 , wherein the inverting amplifier is closer to the far-end capacitor than the near-end capacitor.

4. The apparatus of claim 1 , wherein the inverting amplifier has a trans-conductance greater than five times a critical trans-conductance for startup.

5. The apparatus of claim 1 , wherein the far-end capacitor has a −3 dB cut-off frequency of around 600 MHz at −20 dB/decade roll-off.

6. The apparatus of claim 1 , wherein the first interconnect has a first length, wherein the second interconnect has a second length, wherein the first and second lengths are shorter than a critical length, and wherein the critical length corresponds to an operating frequency of the oscillator.

7. The apparatus of claim 1 , wherein an output of the ADC is a clock.

8. The apparatus of claim 1 , wherein an output of the ADC is a reference clock which is received directly or indirectly by a phase locked loop (PLL).

9. A system comprising:
a memory;
a processor coupled to the memory;
a wireless interface to allow the processor to communicate with another device;
a clock synthesizer having a reference clock node to receive a reference clock; and
a reference clock generator coupled to the clock synthesizer, wherein the reference clock generator is to provide the reference clock, and wherein the reference clock generator is coupled to:
a near-end capacitor coupled to a first interconnect, wherein the first interconnect is coupled to an oscillator;
a far-end capacitor coupled to a second interconnect, wherein the second interconnect is coupled to the oscillator;
a resistor directly conductively coupled to the first and second interconnects to provide a feedback path;
an inverting amplifier coupled to the first and second interconnects; and
a signal conditioning circuitry coupled to the inverting amplifier, wherein the signal conditioning circuitry comprises:
a high pass filter;
a pair of AC coupling capacitors coupled to the high pass filter;
a low pass filter coupled to the pair of AC coupling capacitors; and
an analog to digital converter (ADC) coupled to the low pass filter.

10. The system of claim 9 , wherein the processor is coupled to the oscillator which is positioned off die.

11. The system of claim 9 , wherein the first interconnect has a first length, wherein the second interconnect has a second length, wherein the first and second lengths are shorter than a critical length, and wherein the critical length corresponds to an operating frequency of the oscillator.

12. The system of claim 9 , wherein the resistor is closer to the near-end capacitor than the far-end capacitor.

13. The system of claim 9 , wherein the oscillator comprises a crystal.

14. The system of claim 9 wherein the first and second interconnects are coupled to an inverting amplifier.

15. An apparatus comprising:
a phase locked loop to receive a reference clock;
an analog-to-digital converter (ADC) to generate the reference clock; and
a filter coupled to the ADC, wherein the filter includes a high-pass filter and a low-pass filter coupled to the high-pass-filter, wherein the filter is coupled to:
a first interconnect, wherein the first interconnect is coupled to an oscillator and a near-end capacitor; and
a second interconnect, wherein the second interconnect is coupled to the oscillator and a far-end capacitor, wherein a resistor coupled to the first and second interconnects.

16. The apparatus of claim 15 , wherein:
the resistor is closer to the near-end capacitor than the far-end capacitor; the oscillator comprises a crystal; and
the first and second interconnects are coupled to an inverting amplifier, wherein the inverting amplifier is close to the far-end capacitor than the near-end capacitor.

17. The apparatus of claim 15 , wherein the far-end capacitor has a −3 dB cut-off frequency of around 600 MHz at −20 dB/decade roll-off.

Assignees

• Intel Corp

Inventors

• Yong Khang Choong
• Chong Raymond
• Parthasarathy Ramaswamy
• Hall Stephen
• Kuan Chin Lee

Classifications

• H03B2200/0088

  Reduction of noise · CPC title

• H03L7/06

  using a reference signal applied to a frequency- or phase-locked loop · CPC title

• H03B5/32 Primary

  being a piezoelectric resonator (selection of piezoelectric material H10N30/00) · CPC title