Interconnects having long grains and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11289419-B2
Application number	US-202016942392-A
Country	US
Kind code	B2
Filing date	Jul 29, 2020
Priority date	Nov 21, 2017
Publication date	Mar 29, 2022
Grant date	Mar 29, 2022

Abstract

A method of manufacturing metallic interconnects for an integrated circuit includes forming an interconnect layout including at least one line including a non-diffusing material, forming a diffusing barrier layer on the line, forming an opening extending completely through the diffusing barrier layer and exposing a portion of the line, depositing a diffusing layer on the diffusing barrier layer such that a portion of the diffusing layer contacts the portion of the line, and thermally reacting the diffusing layer to form the metallic interconnects. Thermally reacting the diffusing layer chemically diffuses a material of the diffusing layer into the at least one line and causes at least one crystalline grain to grow along a length of the at least one line from at least one nucleation site defined at an interface between the portions of the diffusing layer and the line.

First claim

What is claimed is:

1. A method of manufacturing metallic interconnects for an integrated circuit, the method comprising:
forming an interconnect layout comprising at least one line, the at least one line comprising a non-diffusing material;
forming a diffusing barrier layer on the at least one line;
forming at least one opening in the diffusing barrier layer, the at least one opening extending completely through the diffusing barrier layer and exposing an exposed portion of the at least one line;
depositing a diffusing layer on the diffusing barrier layer, a portion of the diffusing layer contacting the exposed portion of the at least one line, wherein the diffusing layer has a thickness such that the diffusing layer contains sufficient material to chemically diffuse into substantially an entirety of the at least one line; and
thermally reacting the diffusing layer to form the metallic interconnects, wherein the thermally reacting the diffusing layer chemically diffuses the material of the diffusing layer into substantially the entirety of the at least one line and causes at least one crystalline grain to grow along a length of the at least one line from at least one nucleation site defined at an interface between the portion of the diffusing layer and the exposed portion of the at least one line.

2. The method of claim 1 , wherein the portion of the diffusing layer extends down through the at least one opening in the diffusing barrier layer.

3. The method of claim 1 , wherein the exposed portion of the at least one line extends up through the at least one opening in the diffusing barrier layer.

4. The method of claim 1 , wherein the diffusing barrier layer is an insulator.

5. The method of claim 1 , wherein the non-diffusing material is amorphous silicon.

6. The method of claim 1 , wherein the non-diffusing material is polycrystalline silicon.

7. The method of claim 1 , wherein the diffusing layer comprises a metal or a metal alloy.

8. The method of claim 7 , wherein the metal is nickel and the metal alloy is nickel alloy.

9. The method of claim 1 , further comprising selectively removing unreacted material of the diffusing layer after the thermally reacting the diffusing layer.

10. The method of claim 9 , further comprising selectively removing the diffusing barrier layer after the selectively removing the unreacted material of the diffusing layer.

11. The method of claim 1 , wherein the forming the interconnect layout comprises depositing the non-diffusing material and patterning the non-diffusing material into the at least one line.

12. The method of claim 1 , wherein the forming the interconnect layout comprises conformal deposition of the non-diffusing material into a damascene trench pattern in an insulating layer.

13. The method of claim 1 , further comprising forming at least one landing pad in the at least one line, the at least one landing pad being aligned with the at least opening in the diffusing barrier layer.

14. The method of claim 13 , wherein the at least one landing pad has a first width and a remaining portion of the at least one line has a second width, the first width being greater than the second width.

15. The method of claim 1 , wherein the thermally reacting the diffusing layer is performed at a temperature from approximately 350° C. to approximately 550° C.

16. The method of claim 1 , wherein each crystalline grain of the at least one crystalline grain has a length from approximately 20 nm to approximately 500 nm, the length of each crystalline grain being oriented along a length of at least one of the metallic interconnects.

17. The method of claim 16 , wherein the length of the at least one of the metallic interconnects has a width in a range from approximately 10 nm to approximately 20 nm.

18. The method of claim 1 , wherein the forming the at least one opening in the diffusing barrier layer comprises forming at least two openings in the diffusing barrier layer, the at least two openings being spaced apart along a length of the at least one line.

19. The method of claim 1 , wherein a width of the at least one opening in the diffusing barrier layer is equal to a width of the exposed portion of the at least one line.

20. A method of manufacturing metallic interconnects for an integrated circuit, the method comprising:
forming an interconnect layout comprising at least one line, the at least one line comprising silicon;
forming a diffusing barrier layer on the at least one line;
forming at least one opening in the diffusing barrier layer, the at least one opening extending completely through the diffusing barrier layer and exposing an exposed portion of the at least one line;
depositing a diffusing layer on the diffusing barrier layer, a portion of the diffusing layer filling the at least one opening and contacting the exposed portion of the at least one line; and
thermally reacting the diffusing layer to form the metallic interconnects, wherein the thermally reacting the diffusing layer chemically diffuses a material of the diffusing layer into the at least one line and causes at least one crystalline grain to grow along a length of the at least one line and under the diffusing barrier layer from at least one nucleation site defined at an interface between the portion of the diffusing layer and the exposed portion of the at least one line,
wherein the thermally reacting the diffusing layer silicidizes the silicon in the at least one line.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kittl Jorge A
• Hegde Ganesh
• Simka Harsono

Classifications

• H10W20/4451

  Semiconductor materials, e.g. polysilicon · CPC title

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/066 Primary

  by forming silicides of refractory metals · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title