Electronic substrates having embedded magnetic material using photo-imagable dielectric layers

Patent metadata

Field	Value
Publication number	US-11289263-B2
Application number	US-201715854460-A
Country	US
Kind code	B2
Filing date	Dec 26, 2017
Priority date	Dec 26, 2017
Publication date	Mar 29, 2022
Grant date	Mar 29, 2022

Abstract

An electronic structure may be fabricated comprising an electronic substrate having at least one photo-imageable dielectric layer and an inductor embedded in the electronic substrate, wherein the inductor comprises a magnetic material layer disposed within a via formed in the at least one photo-imageable dielectric layer and an electrically conductive via extending through the magnetic material layer. The electronic structure may further include an integrated circuit device attached to the electronic substrate and the electronic substrate may further be attached to a board, such as a motherboard.

First claim

What is claimed is:

1. An inductor, comprising:
a photo-imageable dielectric layer having a via formed therethrough;
a magnetic material layer disposed within the via of the photo-imageable dielectric layer; and
an electrically conductive via extending through the magnetic material layer, wherein the electrically conductive via comprises an inductor conduct via and a contact, wherein the inductor conductive via and the contact are disposed within the via formed through the at least one photo-imageable dielectric layer, and wherein the magnetic material layer directly contacts the inductor conductive via and the contact.

2. The inductor of claim 1 , wherein the photo-imageable dielectric layer comprises molecular chains selected from the group consisting of diazoketones, diazoalkyl naphthalenes, diazobenzoketones, and indene carboxylic acids.

3. The inductor of claim 1 , wherein the magnetic material layer comprises magnetic particles disposed in a carrier material.

4. An electronic structure, comprising:
an electronic substrate having at least one photo-imageable dielectric layer; and
an inductor embedded in the electronic substrate, wherein the inductor comprises a magnetic material layer disposed within a via formed through the at least one photo-imageable dielectric layer and an electrically conductive via extending through the magnetic material layer, wherein the electrically conductive via comprises an inductor conduct via and a contact, wherein the inductor conductive via and the contact are disposed within the via formed through the at least one photo-imageable dielectric layer, and wherein the magnetic material layer directly contacts the inductor conductive via and the contact.

5. The electronic structure of claim 4 , wherein the photo-imageable dielectric layer comprises molecular chains selected from the group consisting of diazoketones, diazoalkyl naphthalenes, diazobenzoketones, and indene carboxylic acids.

6. The electronic structure of claim 4 , wherein the magnetic material layer comprises magnetic particles disposed in a carrier material.

7. The electronic structure of claim 4 , further comprising an integrated circuit device attached to a first surface of the electronic substrate.

8. The electronic structure of claim 4 , wherein the electronic substrate includes a substrate core.

9. The electronic structure of claim 8 , wherein the substrate core further includes a plurality of through-hole vias.

10. An electronic system, comprising:
a board; and
an electronic package attached to the board, wherein the electronic package comprises:
an electronic substrate having at least one photo-imageable dielectric layer;
an inductor embedded in the electronic substrate, wherein the inductor comprises a magnetic material layer disposed within a via formed in the at least one photo-imageable dielectric layer and an electrically conductive via extending through the magnetic material layer; and
an integrated circuit device electrically attached to the electronic substrate, wherein the electrically conductive via comprises an inductor conduct via and a contact, wherein the inductor conductive via and the contact are disposed within the via formed through the at least one photo-imageable dielectric layer, and wherein the magnetic material layer directly contacts the inductor conductive via and the contact.

11. The electronic system of claim 10 , wherein the photo-imageable dielectric layer comprises molecular chains selected from the group consisting of diazoketones, diazoalkyl naphthalenes, diazobenzoketones, and indene carboxylic acids.

12. The electronic system of claim 10 , wherein the magnetic material comprises magnetic particles disposed in a carrier material.

13. The electronic system of claim 10 , wherein the electronic substrate includes a substrate core.

14. The electronic system of claim 13 , wherein the substrate core further includes forming a plurality of through-hole vias.

15. A method of fabricating an electronic structure, comprising:
forming an electronic substrate having at least one photo-imageable dielectric layer;
forming at least one via through the at least one photo-imageable dielectric layer;
forming a magnetic material layer within the at least one via; and
forming an electrically conductive via extending through the magnetic material layer, wherein the electrically conductive via comprises an inductor conduct via and a contact, wherein the inductor conductive via and the contact are disposed within the via formed through the at least one photo-imageable dielectric layer, and wherein the magnetic material layer directly contacts the inductor conductive via and the contact.

16. The method of claim 15 , wherein forming the electronic substrate having at least one photo-imageable dielectric layer comprises the at least one photo-imageable dielectric layer comprising molecular chains selected from the group consisting of diazoketones, diazoalkyl naphthalenes, diazobenzoketones, and indene carboxylic acids.

17. The method of claim 16 , wherein forming the magnetic material layer comprises forming the magnetic material layer from a material comprising magnetic particles disposed in a carrier material.

18. The method of claim 15 , further comprising electrically attaching an integrated circuit device to the electronic substrate.

19. The method of claim 15 , wherein forming the electronic substrate includes forming a substrate core and wherein at least one photo-imageable dielectric layer is formed on the substrate core.

20. The method of claim 19 , wherein forming the substrate core further includes forming a plurality of through-hole vias.

Assignees

• Intel Corp

Inventors

• Vadlamani Sai
• Chatterjee Prithwish
• Link Lauren A
• Brown Andrew J

Classifications

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H10W70/655

  Fan-out layouts · CPC title