Driver circuit

Patent metadata

Field	Value
Publication number	US-11289046-B2
Application number	US-201916679575-A
Country	US
Kind code	B2
Filing date	Nov 11, 2019
Priority date	Nov 14, 2018
Publication date	Mar 29, 2022
Grant date	Mar 29, 2022

Abstract

The present invention is targeted at suppressing ringing and overvoltage.A driver circuit (200) drives a plurality of loads (Z1 to ZN). A plurality of output terminals (Po1 to PoN) are connected to the plurality of loads (Z1 to ZN). A plurality of drivers (Dr1 to DrN) correspond to the plurality output terminals (Po1 to PON), and generate driving signals (Vo#) applied to the respectively corresponding load (Z#). A plurality of clamp circuits (260_1 to 260_N) correspond to the plurality of drivers (Dr1 to DrN), and include Schottky diodes (SD) connected to input nodes or output nodes of the respectively corresponding drivers (Dr).

First claim

What is claimed is:

1. A driver circuit, driving a plurality of load devices, the driver circuit comprising:
a plurality of output terminals, connected to the plurality of load devices;
a plurality of drivers, corresponding to the plurality of output terminals, generating driving signals applied to the respectively corresponding load devices; and
a plurality of clamp circuits, corresponding to the plurality of drivers, comprising Schottky diodes connected to input nodes or output nodes of the respectively corresponding drivers;
wherein, the driver circuit is integrated on a semiconductor substrate, and each one of the drivers is respectively connected to each one of the corresponding load devices via each one of the corresponding clamp circuits.

2. The driver circuit according to claim 1 , wherein each of the clamping circuit comprises:
an upper-side Schottky diode, provided between the input node or the output node of the corresponding driver and a power line; and
a lower-side Schottky diode, provided between the input node or the output node of the corresponding driver and a ground line.

3. The driver circuit according to claim 1 , further comprising:
a plurality of bypass circuits, corresponding to the plurality of drivers, comprising capacitors connected to the input nodes or the output nodes of the respectively corresponding drivers.

4. The driver circuit according to claim 3 , wherein
the capacitor is a gate capacitor of a metal-oxide-semiconductor (MOS) transistor.

5. The driver circuit according to claim 3 , wherein each of the bypass circuits comprises:
an upper-side capacitor, provided between the input node or the output node of the corresponding driver and a power line; and
a lower-side capacitor, provided between the input node or the output node of the corresponding driver and a ground line.

6. The driver circuit according to claim 1 , wherein
the driver circuit is in a package having a first direction as lengthwise and a second direction as widthwise;
the plurality of output terminals are disposed and aligned in the first direction; and
the driver and the clamp circuit corresponding to one of the output terminals are disposed and aligned in the second direction.

7. The driver circuit according to claim 1 , further comprising:
a plurality of protection circuits, corresponding to the plurality of output terminals, comprising protection diodes connected to the respectively corresponding output terminals.

8. The driver circuit according to claim 1 , wherein each of the plurality of drivers comprises an analog switch.

9. The driver circuit according to claim 1 , wherein each of the plurality of drivers comprises an amplifier.

10. The driver circuit according to claim 1 , wherein each of the plurality of drivers comprises an inverter outputting a high-level voltage and a low-level voltage.

11. The driver circuit according to claim 1 , wherein the driver circuit drives a matrix-type display panel.

12. The driver circuit according to claim 1 , the driver circuit drives a print head.

13. A driver circuit, driving a plurality of load devices, the driver circuit comprising:
a plurality of output terminals, connected to the plurality of load devices;
a plurality of drivers, corresponding to the plurality of output terminals, generating driving signals applied to the respectively corresponding load devices;
a plurality of first diodes, corresponding to the plurality of output terminals, connected to the respectively corresponding output terminals; and
a plurality of clamp circuits, corresponding to the plurality of drivers, comprising second diodes connected to input nodes or output nodes of the respectively corresponding drivers;
wherein, the driver circuit is integrated on a semiconductor substrate, and a forward voltage of the second diode is smaller than that of the first diode, wherein the plurality of first diodes and the plurality of second diodes are disposed within the driver circuit.

14. The driver circuit according to claim 13 , wherein the second diode is a Schottky diode.

15. The driver circuit according to claim 13 , further comprising:
a plurality of bypass circuits, corresponding to the plurality of drivers, comprising capacitors connected to the input nodes or output nodes of the respectively corresponding drivers.

16. A driver circuit, driving a plurality of load devices, the driver circuit comprising:
a plurality of output terminals, connected to the plurality of load devices;
a plurality of drivers, corresponding to the plurality of output terminals, generating driving signals applied the respectively corresponding load devices;
a plurality of clamp circuits, corresponding to the plurality of drivers, connected to input nodes or output nodes of the respectively corresponding drivers; and
a plurality of bypass circuits, corresponding to the plurality of drivers, comprising capacitors connected to input nodes or output nodes of the respectively corresponding drivers;
wherein, the driver circuit is integrated on a semiconductor substrate, and each one of the drivers is respectively connected to each one of the corresponding load devices via each one of the corresponding clamp circuits.

Assignees

• Rohm Co Ltd

Inventors

• Inokuchi Hiroyuki

Classifications

• B41J2/04541 Primary

  Specific driving circuit · CPC title

• G09G2300/089

  Pixel comprising a non-linear two-terminal element in series with each display pixel element, the series comprising also other elements · CPC title

• G09G2310/0291

  Details of output amplifiers or buffers arranged for use in a driving circuit · CPC title

• B41J2/0455

  Details of switching sections of circuit, e.g. transistors · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title