Pixel circuit and display device having the same

Patent metadata

Field	Value
Publication number	US-11289013-B2
Application number	US-202017075066-A
Country	US
Kind code	B2
Filing date	Oct 20, 2020
Priority date	Oct 23, 2019
Publication date	Mar 29, 2022
Grant date	Mar 29, 2022

Abstract

A pixel circuit including a compensation circuit, a writing circuit, a light emitting element, and a power supplying circuit is provided. The compensation circuit comprises a first node, and provides a driving current to the light emitting element according to a voltage of the first node and a system high voltage. The writing circuit provides a data voltage to the compensation circuit according to a first control signal so that the compensation circuit sets the voltage of the first node. The power supplying circuit selectively couples the compensation circuit to the light emitting element, and provides the system high voltage and a system low voltage to the compensation circuit, in which the system low voltage is configured to reset the voltage of the first node. The first control signal and the second control signal are opposite to the first emission signal and the second emission signal, respectively.

First claim

What is claimed is:

1. A pixel circuit, comprising:
a compensation circuit, comprising a first node, and configured to provide a driving current according to a voltage of the first node and a system high voltage;
a writing circuit, configured to provide a data voltage to the compensation circuit according to a first control signal so that the compensation circuit sets the voltage of the first node;
a light emitting element, configured to emit light according to the driving current; and
a power supplying circuit, configured to couple the compensation circuit to the light emitting element according to a first emission signal, configured to provide the system high voltage to the compensation circuit according to a second emission signal, and configured to provide a system low voltage to the compensation circuit according to a second control signal to reset the voltage of the first node,
wherein the first control signal is opposite to the first emission signal, and the second control signal is opposite to the second emission signal,
wherein in a frame period, a time length in which the first control signal having a logic high level is same as a time length in which the second control signal having the logic high level, and a time length in which the first emission signal having a logic low level is same as a time length in which the second emission signal having the logic low level.

2. The pixel circuit of claim 1 , wherein in the frame period, the time length in which the first control signal having the logic high level, the time length in which the second control signal having the logic high level, the time length in which first emission signal having the logic low level, and the time length in which the second emission signal having the logic low level are same as each other.

3. The pixel circuit of claim 1 , wherein the compensation circuit further comprises:
a first input terminal, configured to receive the system high voltage;
a second input terminal, configured to receive the system low voltage; and
a driving transistor, comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the driving transistor is coupled with the first input terminal, the second terminal of the driving transistor is coupled with the second input terminal, and the control terminal of the driving transistor is coupled with the first node,
wherein if the power supplying circuit provides the system high voltage to the compensation circuit, the compensation circuit disconnects the first node from the first input terminal and from the second input terminal, in which a leakage current flows from the first input terminal to the first node, and another leakage current flows from the first node to the second input terminal, so as to stabilized the voltage of the first node.

4. The pixel circuit of claim 1 , wherein the compensation circuit further comprises:
a first input terminal, configured to receive the system high voltage;
a second input terminal, configured to receive the system low voltage;
a driving transistor, comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the driving transistor is coupled with the first input terminal, the second terminal of the driving transistor is coupled with the second input terminal, and the control terminal of the driving transistor is coupled with the first node;
a first switch, comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first switch is coupled with the second input terminal, the second terminal of the first switch is coupled with the first node, and the control terminal of the first switch is configured to receive the first control signal;
a second switch, comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second switch is coupled with the first input terminal, the second terminal of the second switch is coupled with the first node, and the control terminal of the second switch is configured to receive the second control signal; and
a storage capacitor, coupled between the first node and the writing circuit.

5. The pixel circuit of claim 1 , wherein the writing circuit comprises:
a third switch, comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the third switch is coupled with the compensation circuit, the second terminal of the third switch is configured to receive the data voltage, and the control terminal of the third switch is configured to receive the first control signal; and
a fourth switch, comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fourth switch is coupled with the compensation circuit, the second terminal of the fourth switch is configured to receive a reference voltage, and the control terminal of the fourth switch is configured to receive the first emission signal.

6. The pixel circuit of claim 1 , wherein the power supplying circuit comprises:
a fifth switch, comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fifth switch is configured to receive the system high voltage, the second terminal of the fifth switch is coupled with the compensation circuit, and the control terminal of the fifth switch is configured to receive the second emission signal;
a sixth switch, comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the sixth switch is configured to receive the system low voltage, the second terminal of the sixth switch is coupled with the compensation circuit, and the control terminal of the sixth switch is configured to receive the second control signal; and
a seventh switch, comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the seventh switch is coupled with the compensation circuit, the second terminal of the seventh switch is coupled with the light emitting element, and the control terminal of the seventh switch is configured to receive the first emission signal.

7. A display device, comprising:
a gate driving circuit, configured to provide a plurality of control signals and a plurality of emission signals, wherein the plurality of control signals are opposite to the plurality of emission signals, respectively;
a pixel array, coupled with the gate driving circuit, and comprising a plurality of pixel circuits, wherein each of the plurality of pixel circuits comprises:
a compensation circuit, comprising a first node, and configured to provide a driving current according to a voltage of the first node and a system high voltage;
a writing circuit, configured to provide a data voltage to the compensation circuit according to a first control signal of the plurality of control signals, so that the compensation circuit sets the voltage of the first node;
a light emitting element, configured to emit lights according to the driving current; and
a power supplying circuit, configured to conduct the compensation circuit to the light emitting element according to a first emission signal of the plurality of emission signals, configured to provide the system high voltage to the compensation circuit according to a second emission signal of the plurality of emission signals, and configured to provide a system low voltage to the compensation circuit according to a second control signal of the plurality of control signals so as to reset the voltage of the first node; and

a source driving circuit, coupled with the pixel array, and configured to provide the data voltage,
wherein in a frame period, a time length in which the first control signal having a logic high level is s

Assignees

• Au Optronics Corp

Inventors

• Lin Chih-Lung
• Lai Po-Cheng
• Chu Ting-Ching
• Lai Po-Chun
• Cheng Mao-Hsun

Classifications

• G09G3/3208 Primary

  organic, e.g. using organic light-emitting diodes [OLED] · CPC title

• G09G2330/028

  Generation of voltages supplied to electrode drivers in a matrix display other than LCD · CPC title

• G09G2320/045

  Compensation of drifts in the characteristics of light emitting or modulating elements · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

• G09G3/3233 Primary

  with pixel circuitry controlling the current through the light-emitting element · CPC title