High voltage gain switched capacitor filter integration

Patent metadata

Field	Value
Publication number	US-11288461-B2
Application number	US-201716633223-A
Country	US
Kind code	B2
Filing date	Jul 27, 2017
Priority date	Jul 27, 2017
Publication date	Mar 29, 2022
Grant date	Mar 29, 2022

Abstract

A method of operating switched capacitor filter integration circuits by pre-charging a final filter capacitor thereof with the final full voltage gain value during a first subframe to obtain an enhanced signal to noise ratio without changes to the circuit or components thereof.

First claim

What is claimed is:

1. A method of operating a switched capacitor filter subframe integration circuit comprising:
on a switched capacitor filter subframe integration circuit comprising a split switch, a sum switch, an integration capacitor, a split capacitor, and a sum capacitor;
closing the split switch and the sum switch, thereby resetting the integration capacitor, the split capacitor, and the sum capacitor;
integrating a first subframe across the integration capacitor, the split capacitor, and the sum capacitor simultaneously;
resetting the integration capacitor and the split capacitor;
integrating a second subframe on the integration capacitor and the split capacitor;
opening the split switch;
closing the sum switch, thereby allowing the charge on the split capacitor to flow into the sum capacitor;
repeating the step of integrating the second subframe as many times as desired to complete subframe integration with desired levels of voltage gain and noise;
wherein an integration time of the first subframe is longer than that of subsequent subframes in accordance with the ratio:
Fs int=( C int +Cs p +C sum )/( C int +C sp)

Where:
F sint =First Subframe Interval (ms)
C int =Capacitance of the integration capacitor
C sp =Capacitance of the split capacitor
C sum =Capacitance of the sum capacitor.

2. The method of claim 1 wherein the sum capacitor is larger than the integration capacitor and the split capacitor.

3. The method of claim 1 wherein a combined capacitance of the integration capacitor, the split capacitor, and the sum capacitor is double that of the integration and the split.

4. The method of claim 1 wherein the integration time is scaled based on the size of the sum capacitor relative to the integration and the split capacitor to maintain a desired gain.

5. The method of claim 1 wherein the integration time is increased proportionately to the increase in capacitance to the switched capacitor filter subframe integration circuit.

6. A method of operating a switched capacitor filter subframe integration circuit comprising:
during a first integration, setting a voltage of a sum capacitor equal to what is seen on an integration capacitor,
wherein an integration time of a first subframe is longer than that of subsequent subframes in accordance with the ratio:
Fs int=( C int +C sp +C sum )/( C int +C sp)

Where:
F sint =First Subframe Interval (ms)
C int =Capacitance of the integration capacitor
C sp =Capacitance of a split capacitor
C sum =Capacitance of the sum capacitor.

7. The method of claim 6 wherein the sum capacitor is larger than the integration capacitor and the split capacitor.

8. The method of claim 6 wherein a combined capacitance of the integration capacitor, the split capacitor, and the sum capacitor present on the integration circuit is double that of the integration capacitor and the split capacitor present thereon.

9. The method of claim 6 wherein the integration time is scaled based on the size of the sum capacitor relative to the integration capacitor and the split capacitor present on the integration circuit to maintain a desired gain.

10. The method of claim 6 wherein the integration time is increased proportionately to increase in capacitance.

11. A method of operating a switched capacitor filter subframe integration circuit comprising:
on a switched capacitor filter subframe integration circuit comprising a split switch, a sum switch, an integration capacitor, a split capacitor, and a sum capacitor, wherein the switched capacitor filter subframe integration circuit is fixed to and in operative communication with a pixel;
closing the split switch and the sum switch, thereby resetting the integration capacitor, the split capacitor, and the sum capacitor;
integrating a first subframe across the integration capacitor, the split capacitor, and the sum capacitor simultaneously;
resetting the integration capacitor and the split capacitor;
integrating a second subframe on the integration capacitor and the split capacitor;
opening the split switch;
closing the sum switch, thereby allowing the charge on the split capacitor to flow into the sum capacitor;
repeating the integration of the second subframe by repeating the steps of opening the split switch and closing the sum switch as many times as desired to complete subframe integration with desired levels of voltage gain and noise,
wherein an integration time of the first subframe is longer than that of subsequent subframes in accordance with the ratio:
Fs int=( C int +C sp +C sum )/( C int +C sp)

Where:
F sint =First Subframe Interval (ms)
C int =Capacitance of the integration capacitor
C sp =Capacitance of the split capacitor
C sum =Capacitance of the sum capacitor.

12. The method of claim 11 wherein the sum capacitor is larger than the integration capacitor and the split capacitor.

13. The method of claim 11 wherein a combined capacitance of the integration capacitor, the split capacitor, and the sum capacitor is double that of the integration and the split capacitor.

14. The method of claim 11 wherein the integration time is scaled based on the size of the sum capacitor relative to the integration and the split capacitor to maintain a desired gain.

15. The method of claim 11 wherein the integration time is increased proportionately to the increase in capacitance to the switched capacitor filter subframe integration circuit.

Assignees

• Bae Sys Inf & Elect Sys Integ

Inventors

• Hairston Allen W

Classifications

• G06G7/184 Primary

  using capacitive elements · CPC title

• G06F7/64

  Digital differential analysers, i.e. computing devices for differentiation, integration or solving differential or integral equations, using pulses representing increments; Other incremental computing devices for solving difference equations (G06F7/70 takes precedence; differential analysers using hybrid computing techniques G06J1/02 {; DDA application in numerical control G05B19/18}) · CPC title