Coherency locking schemes

Patent metadata

Field	Value
Publication number	US-11287987-B2
Application number	US-202016809058-A
Country	US
Kind code	B2
Filing date	Mar 4, 2020
Priority date	Mar 4, 2020
Publication date	Mar 29, 2022
Grant date	Mar 29, 2022

Abstract

Methods, systems, and devices for coherency locking are described in which different types of writes have different coherency locking schemes. The types of writes can be associated with different sources of write commands, such as external commands from a host system or internal commands from a garbage collection procedure. Coherency locking can be performed for external write commands received from a host system, while coherency locking is not performed for internal write commands. If an internal write is received for data that has been previously written at a prior location, a write to one or more physical memory devices can be performed and, once an acknowledgment is received that the write is complete, an update to a mapping table with the new location of the data is performed.

First claim

What is claimed is:

1. A method, comprising:
receiving, at a controller for a memory sub-system, a first write command from a host device to write a first block of data at a first memory address of a memory device of the memory sub-system;
locking a first coherency of the first memory address responsive to receiving the first write command; and
receiving a second write command generated by a processing core of the controller to write a second block of data at a second memory address of the memory device, wherein a second coherency of the second memory address is maintained in an unlocked state after receiving the second write command.

2. The method of claim 1 , further comprising:
updating, responsive to completing the second write command, a mapping record to indicate the second block of data is located at the second memory address, wherein the mapping record indicates that the second block of data is located at a prior memory address prior to the updating.

3. The method of claim 2 , further comprising:
updating, responsive to receiving the first write command, the mapping record to indicate the first block of data is located at the first memory address.

4. The method of claim 3 , further comprising:
receiving a read command to read the first block of data; and
sending a coherency lock indication responsive to the read command.

5. The method of claim 1 , wherein the first write command and the second write command are received at a first processing core of the controller, and the second write command is received from a second processing core of the controller.

6. The method of claim 5 , wherein the second processing core of the controller executes a garbage collection procedure associated with the second write command.

7. The method of claim 1 , wherein the locking the first coherency comprises:
providing a coherency lock command and the first memory address to a coherency block of the controller.

8. A method comprising:
receiving, at a controller for a memory sub-system, a first write command from a host device to write a first block of data at a first memory address of a memory device of the memory sub-system;
locking a first coherency of the first memory address responsive to receiving the first write command;
receiving, from a processing core of the controller, a second write command to write a second block of data at a second memory address of the memory device, wherein a second coherency of the second memory address is maintained in an unlocked state after receiving the second write command;
receiving, a mapping record for the second block of data and a read command to read the second block of data;
reading a prior memory address to provide the second block of data; and
updating, responsive to completing the second write command, the mapping record to indicate the second block of data is located at the second memory address, wherein the mapping record indicates that the second block of data is located at the prior memory address prior to the updating.

9. A system, comprising:
a plurality of memory components; and
a processing device operatively coupled with the plurality of memory components, the processing device configured to:
receive a first write command from a device that is external to the system, the first write command to write a first block of data at a first memory address of the plurality of memory components;
lock a first coherency of the first memory address responsive to receiving the first write command;
receive a second write command generated by a sub-component of the system, the second write command to write a second block of data at a second memory address of the plurality of memory components; and
maintain a second coherency of the second memory address in an unlocked state after receiving the second write command.

10. The system of claim 9 , further comprising:
the processing device further configured to:
update, responsive to completing the second write command, a mapping record to indicate the second block of data is located at the second memory address, wherein the mapping record indicates that the second block of data is located at a prior memory address prior to the update.

11. The system of claim 10 , further comprising:
the processing device further configured to:
update, responsive to receiving the first write command, the mapping record to indicate the first block of data is located at the first memory address.

12. The system of claim 11 , further comprising:
the processing device further configured to:
receive a read command to read the first block of data; and
send a coherency lock indication responsive to the read command.

13. The system of claim 9 , wherein the first write command and the second write command are received at a first processing core of the processing device, and the second write command is received from a second processing core of the processing device.

14. The system of claim 13 , wherein the second processing core executes a garbage collection procedure associated with the second write command.

15. A system, comprising:
a plurality of memory components; and
a processing device operatively coupled with the plurality of memory components, the processing device configured to:
receive a first write command from a device that is external to the system, the first write command to write a first block of data at a first memory address of the plurality of memory components;
lock a first coherency of the first memory address responsive to receiving the first write command;
receive a second write command from a sub-component of the system, the second write command to write a second block of data at a second memory address of the plurality of memory components;
maintain a second coherency of the second memory address in an unlocked state after receiving the second write command;
receive, a mapping record for the second block of data and a read command to read the second block of data;
read a prior memory address to provide the second block of data; and
update, responsive to completing the second write command, the mapping record to indicate the second block of data is located at the second memory address, wherein the mapping record indicates that the second block of data is located at the prior memory address prior to the update.

16. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
receive a first write command from an external device to write a first block of data at a first memory address of a memory device;
lock a first coherency of the first memory address responsive to receiving the first write command; and
receive a second write command generated by an internal component of the processing device to write a second block of data at a second memory address of the memory device, wherein a second coherency of the second memory address remains in an unlocked state after receiving the second write command.

17. The non-transitory computer-readable storage medium of claim 16 , wherein the processing device is further configured to:
update, responsive to completing the second write command, a mapping record to indicate the second block of data is located at the second memory address, wherein the mapping record indicates that the second block of data is located at a prior memory address prior to the update.

18. The non-transitory computer-readable storage medium of claim 17 , wherein the processing device is further configured to:
update, responsive to the

Assignees

• Micron Technology Inc

Inventors

• Li Yun
• Traver John

Classifications

• G06F3/0685

  Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays · CPC title

• G06F3/0619 Primary

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0629

  Configuration or reconfiguration of storage systems · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title