Signal combiner

Patent metadata

Field	Value
Publication number	US-11283409-B2
Application number	US-201916557961-A
Country	US
Kind code	B2
Filing date	Aug 30, 2019
Priority date	Aug 30, 2019
Publication date	Mar 22, 2022
Grant date	Mar 22, 2022

Abstract

In certain aspects, a receiver includes first amplifiers, wherein each one of the first amplifiers comprises an input and an output. The receiver also includes second amplifiers, wherein each one of the second amplifiers comprises an input and an output, and the outputs of the second amplifiers are coupled to a combining node. The receiver also includes transmission lines, wherein each one of the transmission lines is coupled between the output of a respective one of the first amplifiers and the input of a respective one of the second amplifiers. The receiver further includes a load coupled to the combining node, and receiver elements, wherein each one of the receiver elements comprises an input and an output, and the output of each one of the receiver elements is coupled to the input of a respective one of the first amplifiers.

First claim

What is claimed is:

1. A receiver, comprising:
first amplifiers, wherein each one of the first amplifiers comprises an input and an output;
second amplifiers, wherein each one of the second amplifiers comprises an input and an output, and the outputs of the second amplifiers are coupled to a combining node;
transmission lines, wherein each one of the transmission lines is coupled between the output of a respective one of the first amplifiers and the input of a respective one of the second amplifiers;
a load coupled to the combining node;
receiver elements, wherein each one of the receiver elements comprises an input and an output, and the output of each one of the receiver elements is coupled to the input of a respective one of the first amplifiers;
antennas, wherein the input of each one of the receiver elements is coupled to a respective one of the antennas, and
a local oscillator configured to generate a local oscillator signal, wherein each one of the receiver elements comprises a mixer configured to mix a signal received at the mixer with the local oscillator signal or a signal based on the local oscillator signal.

2. The receiver of claim 1 , wherein each one of the receiver elements comprises a phase shifter configured to:
receive a signal from the respective one of the antennas; and
shift a phase of the signal from the respective one of the antennas by a respective phase shift to generate a phase-shifted signal.

3. The receiver of claim 2 , further comprising a phase-shift controller, wherein the antennas are part of a phased antenna array, and, for each one of the receiver elements, the phase-shift controller is configured to set the respective phase shift based on a receive direction for the phased antenna array.

4. The receiver of claim 2 ,
wherein each mixer is configured to:
receive the phase-shifted signal from the respective phase shifter; and
mix the phase-shifted signal from the respective phase shifter with the local oscillator signal.

5. The receiver of claim 1 ,
wherein each one of the receiver elements comprises:
a phase shifter configured to receive the local oscillator signal and shift a phase of the local oscillator signal by a respective phase shift to generate a respective phase-shifted local oscillator signal; and
wherein each mixer is configured to:
receive a signal from the respective one of the antennas; and
mix the signal from the respective one of the antennas with the respective phase-shifted local oscillator signal.

6. The receiver of claim 1 , wherein each one of the second amplifiers is a common gate amplifier.

7. The receiver of claim 6 , wherein each one of the second amplifiers has an electronically adjustable channel width.

8. The receiver of claim 7 , wherein:
each one of the second amplifiers comprises:
multiple branches coupled between the combining node and the respective one of the transmission lines, wherein each one of the multiple branches comprises a transistor and a switch coupled in series, and each one of the multiple branches is enabled by closing the respective switch; and

the receiver further comprises a control circuit configured to set the channel width of each one of the second amplifiers by controlling a number of the respective branches that are enabled.

9. The receiver of claim 7 , wherein:
each one of the second amplifiers comprises:
multiple branches coupled between the combining node and the respective one of the transmission lines, wherein each one of the multiple branches comprises a transistor and a switch configured to selectively couple a gate of the transistor to a gate bias voltage or a ground, and each one of the multiple branches is enabled by setting the respective switch to couple the gate of the respective transistor to the gate bias voltage; and

the receiver further comprises a control circuit configured to set the channel width of each one of the second amplifiers by controlling a number of the respective branches that are enabled.

10. The receiver of claim 9 , wherein the switch in each one of the multiple branches comprises a respective single-pole-two-throw switch.

11. The receiver of claim 7 , further comprising:
a register configured to store, for each one of the second amplifiers, a respective channel width value; and
a control circuit configured to set the channel width of each one of the second amplifiers based on the respective channel width value in the register.

12. The receiver of claim 11 , wherein the channel width value for a first one of the second amplifiers is different from the channel width value for a second one of the second amplifiers.

13. The receiver of claim 1 , wherein each one of the first amplifiers is a current amplifier.

14. The receiver of claim 13 , wherein each one of the first amplifiers comprises:
a current source;
a current mirror comprising an input and an output, wherein the input of the current mirror is coupled to the current source and the input of the first amplifier, and the output of the current mirror is coupled to the respective one of the transmission lines.

15. The receiver of claim 14 , wherein the current mirror of each one of the first amplifiers has an electronically adjustable current-mirror ratio.

16. The receiver of claim 15 , further comprising:
a register configured to store, for each one of the first amplifiers, a respective current gain value; and
a control circuit configured to set the current-mirror ratio of the current mirror of each one of the first amplifiers based on the respective current gain value in the register.

17. The receiver of claim 16 , wherein the current gain value for a first one of the first amplifiers is different from the current gain value for a second one of the first amplifiers.

18. The receiver of claim 14 , wherein the current mirror of each one of the first amplifiers comprises:
an input transistor comprising a drain coupled to the input of the current mirror, a gate coupled to the input of the current mirror, and a source coupled to a ground; and
an output transistor comprises a drain coupled to the output of the current mirror, a gate coupled to the gate of the input transistor, and a source coupled to the ground.

19. The receiver of claim 18 , wherein, for each one of the first amplifiers, the input transistor of the respective current mirror has an electronically adjustable channel width.

20. The receiver of claim 18 , wherein, for each one of the first amplifiers, the output transistor of the respective current mirror has an electronically adjustable channel width.

21. The receiver of claim 1 , wherein a first one of the transmission lines has a length that is at least 20 percent longer than a length of a second one of the transmission lines.

22. A receiver, comprising:
first amplifiers, wherein each one of the first amplifiers comprises an input and an output;
second amplifiers, wherein each one of the second amplifiers comprises an input and an output, and the outputs of the second amplifiers are coupled to a combining node;
transmission lines, wherein each one of the transmission lines is coupled between the output of a respective one of the first amplifiers and the input of a respective one of the second amplifiers;
a load coupled to the combining node; and
receiver elements, wherein each one of the receiver elements comprises an input and an output, and the output of each one of the receiver elements is coupled to the input of a respective one o

Assignees

• Qualcomm Inc

Inventors

• Leung Lai Kan
• Yu Xinmin
• Patel Chirag Dipak
• Rangarajan Rajagopalan

Classifications

• H01P1/2133

  using coaxial filters (H01P1/2131, H01P1/2136 take precedence) · CPC title

• H04B1/40

  Circuits · CPC title

• H03F3/211

  using a combination of several amplifiers (H03F3/60 takes precedence) · CPC title

• H03F1/0288 Primary

  using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers · CPC title

• H03F3/72

  Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal · CPC title