Low voltage feedforward current assist ethernet line driver

Patent metadata

Field	Value
Publication number	US-11283408-B2
Application number	US-201816225043-A
Country	US
Kind code	B2
Filing date	Dec 19, 2018
Priority date	Sep 10, 2014
Publication date	Mar 22, 2022
Grant date	Mar 22, 2022

Abstract

Described examples include Ethernet physical layer (PHY) interface integrated circuits with transmit interface circuitry for transmitting data to an Ethernet network through a magnetic interface, which includes a voltage mode first amplifier with an output that generates a first voltage signal from a supply voltage according to a data input signal. The transmit interface circuit also includes a feedforward second amplifier circuit with an output stage that operates in a first mode to generate a current signal from the supply voltage according to the first voltage signal and to provide the current signal to the first amplifier output to boost a peak voltage at the output above the supply voltage to facilitate support for higher peak signal voltage swings for 10Base-T applications while using 2.5 volt or other low voltage supply levels.

First claim

What is claimed is:

1. A transceiver circuit comprising:
a transmission data terminal;
a transmission voltage terminal;
a first amplifier having a first input coupled to the transmission data terminal, and a first output coupled to the transmission voltage terminal;
a second amplifier having a second input coupled to the first output of the first amplifier, and a second output;
a current mirror having a voltage input coupled to the second output and a current output coupled to the transmission voltage terminal; and
wherein,
the first output is configured to deliver a first output voltage within a supply voltage range;
the second output is configured to deliver a second output voltage within the supply voltage range; and
the transmission voltage terminal is configured to receive a primary voltage beyond the supply voltage range, the primary voltage is based on the first output voltage boosted by a current from the current output, the current is based on the second output voltage.

2. The transceiver circuit of claim 1 , further comprising:
a conductor having a terminal resistance coupled between the first output and the transmission voltage terminal.

3. The transceiver circuit of claim 2 , wherein the conductor is coupled between the first output and the current output.

4. The transceiver circuit of claim 1 , further comprising:
a mode control terminal configured to receive an enable signal, the enable signal configured to enable the second amplifier during a first mode, and disable the second amplifier during a second mode.

5. The transceiver circuit of claim 4 , wherein:
the first mode is associated with a 10Base-Te Ethernet data transmission; and
the second mode is associated with a 100Base-T Ethernet data transmission or a 1000Base-T Ethernet data transmission.

6. The transceiver circuit of claim 1 , wherein the supply voltage range is less than 3V, and the primary voltage is greater than 3V.

7. The transceiver circuit of claim 1 , wherein:
the first output includes a first non-inverting output, and a first inverting output;
the second input includes a second non-inverting input coupled to the first inverting output, and a second inverting input coupled to the first non-inverting output.

8. The transceiver circuit of claim 7 , wherein:
the second output includes a second non-inverting output coupled to the second inverting input, and a second inverting output coupled to the second non-inverting input.

9. The transceiver circuit of claim 8 , further comprising:
a resistor coupled between the second non-inverting output and the second inverting output;
a first feedback path coupled between the second non-inverting output and the second inverting input, the first feedback path includes a first feedback resistor, and a first feedback capacitor coupled in parallel with the first feedback resistor; and
a second feedback path coupled between the second inverting output and the second non-inverting input, the second feedback path includes a second feedback resistor, and a second feedback capacitor coupled in parallel with the second feedback resistor.

10. The transceiver circuit of claim 9 , wherein:
the resistor is configured to conduct a different current based on a differential voltage between the first non-inverting output and the first inverting output;
the current mirror is configured to generate an output current mirroring the differential current; and
the output current is configured to boost the differential voltage at the transmission voltage terminal.

11. The transceiver circuit of claim 8 , wherein the current mirror includes:
a first current mirror having a first voltage input of the voltage input coupled to the second non-inverting output, a first current output of the current output coupled to the first non-inverting output; and
a second current mirror having a second voltage input of the voltage input coupled to the second inverting output, a second current output of the current output coupled to the first inverting output.

12. A transceiver circuit comprising:
a first terminal configured to receive a transmission data signal;
a second terminal configured to deliver a transmission voltage;
a first amplifier configured to deliver a first output voltage based on the transmission data signal, the first output voltage within a supply voltage range;
a second amplifier configured to deliver a second output voltage based on the first output voltage, the second output voltage within the supply voltage range; and
a current mirror configured to generate a current based on the second output voltage, the current routing to boost the transmission voltage beyond the first output voltage at the second terminal.

13. The transceiver circuit of claim 12 , further comprising:
a third terminal configured to receive an enable signal, the enable signal configured to enable the second amplifier during a first mode, and disable the second amplifier during a second mode.

14. The transceiver circuit of claim 13 , wherein:
the first mode is associated with a 10Base-Te Ethernet data transmission; and
the second mode is associated with a 100Base-T Ethernet data transmission or a 1000Base-T Ethernet data transmission.

15. The transceiver circuit of claim 12 , wherein:
the first amplifier includes a first input coupled to the first terminal, and a first output coupled to the second terminal;
the second amplifier having a second input coupled to the first output of the first amplifier, and a second output; and
the current mirror having a voltage input coupled to the second output and a current output coupled to the second terminal.

16. A transceiver circuit comprising:
a first terminal configured to receive a transmission data signal;
a second terminal configured to deliver a transmission voltage;
a first amplifier configured to deliver a first output voltage based on the transmission data signal, the first output voltage within a supply voltage range;
a second amplifier selectively enabled to deliver a second output voltage based on the first output voltage, the second output voltage within the supply voltage range; and
a current mirror configured to generate a current based on the second output voltage, the current routing to boost the transmission voltage beyond the first output voltage at the second terminal.

17. The transceiver circuit of claim 16 , further comprising:
a third terminal configured to receive an enable signal, the enable signal configured to enable the second amplifier during a first mode, and disable the second amplifier during a second mode.

18. The transceiver circuit of claim 17 , wherein:
the first mode is associated with a 10Base-Te Ethernet data transmission; and
the second mode is associated with a 100Base-T Ethernet data transmission or a 1000Base-T Ethernet data transmission.

19. The transceiver circuit of claim 16 , wherein:
the first amplifier includes a first input coupled to the first terminal, and a first output coupled to the second terminal;
the second amplifier having a second input coupled to the first output of the first amplifier, and a second output; and
the current mirror having a voltage input coupled to the second output and a current output coupled to the second terminal.

Assignees

• Texas Instruments Inc

Inventors

• Seth Sumantra
• Ramachandran Ashwin
• Ghorpade Gururaj

Classifications

• H03F1/0277 Primary

  Selecting one or more amplifiers from a plurality of amplifiers · CPC title

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title

• H03F3/30

  Single-ended push-pull {[SEPP]} amplifiers {(single-ended sense amplifiers G11C7/067)}; Phase-splitters therefor · CPC title

• H03F2200/513

  the amplifier being made for low supply voltages · CPC title

• H03F2203/45116

  Feedback coupled to the input of the differential amplifier · CPC title