Fault current mitigation method and system for solid state circuit breaker

Patent metadata

Field	Value
Publication number	US-11283258-B2
Application number	US-202016867640-A
Country	US
Kind code	B2
Filing date	May 6, 2020
Priority date	Dec 10, 2018
Publication date	Mar 22, 2022
Grant date	Mar 22, 2022

Abstract

A solid state circuit breaker apparatus includes a solid state switch, a current sensor, and a control circuit. The control circuit is programmed to operate the solid state switch by, in response to receipt of a signal from the current sensor indicating that an overcurrent condition exists: (i) using pulse width modulation to generate a set of control pulses; and (ii) using the control pulses to trigger the solid state switch to open and close in a pattern that corresponds to the control pulses, and thus limit an amount of let-through current that the solid state switch may pass to a load. The amount of let-through current that the solid state switch may pass to the load may be, for example, a threshold level above which the overcurrent condition will exist.

First claim

The invention claimed is:

1. A solid state circuit breaker apparatus comprising:
a solid state switch;
a current sensor; and
a control circuit,
wherein the control circuit is programmed to operate the solid state switch by, in response to receipt of a signal from the current sensor indicating that an overcurrent condition exists:
using pulse width modulation to generate a set of control pulses at a frequency, wherein the frequency is programmed into the control circuit,
using the control pulses to trigger the solid state switch to open and close in a pattern that corresponds to the control pulses, and thus limiting an amount of let-through current that the solid state switch may pass to a load, and
determining a trip time of the solid state switch based on a level of the let-through current that the current sensor is detecting.

2. The circuit breaker apparatus of claim 1 , wherein the control circuit is programmed to determine the trip time of the solid state switch based also on the frequency for the control pulses.

3. The circuit breaker apparatus of claim 1 , wherein the control circuit comprises:
a microprocessor that is configured to generate the set of control pulses;
a gate drive circuit that is configured to receive the control pulses from the microprocessor and use the control pulses to trigger the solid state switch to open and close according to the pattern; and
a hardware trigger circuit that is electrically connected to the current sensor and the gate drive circuit, and that is configured to:
receive the signal from the current sensor indicating that the overcurrent condition exists, and
send a trigger signal to the gate drive circuit to open the solid state switch.

4. The circuit breaker apparatus of claim 1 , wherein the amount of let-through current that the solid state switch may pass to the load is a threshold level above which the overcurrent condition will exist.

5. The circuit breaker apparatus of claim 1 , wherein the apparatus does not monitor current profile through the circuit breaker apparatus when the control pulses are triggering the solid state switch to open and close.

6. A transformer apparatus with a solid state circuit breaker apparatus, the transformer apparatus comprising:
a transformer;
a conductive path leading from the transformer to a load output;
a solid state switch in the conductive path;
a current sensor positioned in the conductive path between the transformer and the solid state switch; and
a control circuit,
wherein the control circuit is programmed to operate the solid state switch by, in response to receipt of a signal from the current sensor indicating that an overcurrent condition exists:
using pulse width modulation to generate a set of control pulses at a frequency, wherein the frequency is programmed into the control circuit,
using the control pulses to trigger the solid state switch to open and close in a pattern that corresponds to the control pulses, and thus limit an amount of let-through current that the solid state switch may pass to a load, and
determining a trip time of the solid state switch based on a level of the let-through current that the current sensor is detecting.

7. The transformer apparatus of claim 6 , wherein the control circuit is programmed to determine the trip time of the solid state switch based also on the frequency for the control pulses.

8. The transformer apparatus of claim 6 , wherein the control circuit comprises:
a microprocessor that is configured to generate the set of control pulses;
a gate drive circuit that is configured to receive the control pulses from the microprocessor and use the control pulses to trigger the solid state switch to open and close according to the pattern; and
a hardware trigger circuit that is electrically connected to the current sensor and the gate drive circuit, and that is configured to:
receive the signal from the current sensor indicating that the overcurrent condition exists, and
send a trigger signal to the gate drive circuit to open the solid state switch.

9. The transformer apparatus of claim 6 , wherein the amount of let-through current that the solid state switch may pass to the load is a threshold level above which the overcurrent condition will exist.

10. The method of claim 9 , further comprising determining a trip time for the solid state switch based on the level of the current that the current sensor is detecting.

11. The transformer apparatus of claim 6 , wherein the apparatus does not monitor current profile through the solid state switch when the control pulses are triggering the solid state switch to open and close.

12. A method for controlling a solid state circuit breaker system to limit current to a load output in overcurrent conditions, the method comprising:
operating a circuit having a conductive path between a power source and a load output and also having a solid state switch in the conductive path;
by a current sensor, monitoring a level of current through the conductive path and sending a signal to the control circuit indicating that an overcurrent condition exists;
by a control circuit:
determining a frequency for a set of control pulses based on a maximum interruption current level of the solid state circuit breaker apparatus and circuit power factor, and
upon receiving the signal from the current sensor, using pulse width modulation to generate the set of control pulses at the frequency; and

by the gate drive circuit, using the set of control pulses to trigger the solid state switch to open and close in a pattern that corresponds to the control pulses, wherein the opening and closing of the solid state switch limits a level of let-through current that the solid state switch passes to the load output.

13. The method of claim 12 , further comprising:
by the control circuit, using the set of control pulses to trigger the solid state switch to open and close at the frequency, wherein the frequency controls the level of let-through current that the solid state switch passes to the load output.

14. The method of claim 12 , further comprising determining a trip time of the solid state switch based on the frequency for the control pulses.

15. The method of claim 12 , wherein:
the control circuit comprises:
a microprocessor,
a gate drive circuit that is electrically connected to the microprocessor and to the solid state switch, and
a hardware trigger circuit that is electrically connected to the current sensor and to the gate drive circuit; and
wherein:
generating the set of control pulses is performed by the microprocessor;
using the set of control pulses to trigger the solid state switch to open and close in the pattern is performed by the gate drive circuit, and
the method further comprises, by the hardware trigger circuit, sending a trigger signal to the gate drive circuit to open the solid state switch in response to receiving the signal from the current sensor indicating that the overcurrent condition exists.

16. The method of claim 12 , wherein the amount of let-through current that the solid state switch passes to the load output is a threshold level above which the overcurrent condition will exist.

17. The method of claim 12 , further comprising dynamically determining the amount of let-through current that the solid state switch may pass to the load output as perspective fault current of the solid state switch.

18. The method of claim 12 , further comprising not monitoring current profile through the circuit when the control pulses are triggering

Assignees

• Eaton Intelligent Power Ltd

Inventors

• Zhou Xin
• Russoniello Ruppert
• Carlson Brian E

Classifications

• H02H3/025 Primary

  Disconnection after limiting, e.g. when limiting is not sufficient or for facilitating disconnection · CPC title

• G05F1/462

  as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic · CPC title

• H02H9/025 Primary

  Current limitation using field effect transistors · CPC title

• H02H3/08

  responsive to excess current (responsive to abnormal temperature caused by excess current H02H5/04) · CPC title

• H02H9/002

  limiting inrush current on switching on of inductive loads subjected to remanence, e.g. transformers · CPC title