Semiconductor device having multiple electrostatic discharge (ESD) paths

Patent metadata

Field	Value
Publication number	US-11282831-B2
Application number	US-201916575091-A
Country	US
Kind code	B2
Filing date	Sep 18, 2019
Priority date	Sep 18, 2019
Publication date	Mar 22, 2022
Grant date	Mar 22, 2022

Abstract

A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a first well of a first type, disposed on the substrate;
a first doped region of the first type, disposed in the first well, wherein the first doped region is configured as a first terminal of a first diode and is coupled to a first voltage terminal configured to receive a first supply voltage;
a second doped region of a second type disposed in the first well, wherein the second doped region is configured as a second terminal of the first diode and is coupled to an input/output (I/O) pad;
a second well of the second type disposed on the substrate and adjacent to the first well;
a third doped region of the first type, disposed in the second well, wherein the third doped region is configured as a first terminal of a second diode and is coupled to a second voltage terminal configured to receive a second supply voltage; and
a fourth doped region of the second type disposed in the second well, wherein the fourth doped region is configured as a second terminal of the second diode and is coupled to the second voltage terminal;
wherein the first diode, the first voltage terminal, and a clamp circuit coupled between the first voltage terminal and the second voltage terminal are configured as a first electrostatic discharge (ESD) path between the I/O pad and the second voltage terminal, and
wherein the second doped region, the first well, the substrate, the second well, and the third doped region are configured as a second ESD path between the I/O pad and the second voltage terminal.

2. The semiconductor device of claim 1 , further comprising:
a third well of the second type, disposed on the substrate and adjacent to the first well;
a fifth doped region of the first type, disposed in the third well, wherein the fifth doped region is configured as a first terminal of a third diode and is coupled to the I/O pad; and
at least one sixth doped region of the second type, disposed in the third well, wherein the at least one sixth doped region is configured as a second terminal of the third diode and is coupled to the second voltage terminal.

3. The semiconductor device of claim 2 , wherein the first to third wells, the first to fifth doped regions, and the at least one sixth doped regions are configured in a cell of a layout of the semiconductor device, and the semiconductor device further comprises:
a plurality of the cells arranged in an array.

4. The semiconductor device of claim 2 , wherein the at least one sixth doped region comprises:
a plurality of sixth doped regions each having a strap configuration in a plain view, wherein the plurality of sixth doped regions are arranged along a first direction.

5. The semiconductor device of claim 4 , wherein the first to third wells, the first to fifth doped regions, and the plurality of sixth doped regions are configured in a cell of a layout of the semiconductor device, and the semiconductor device further comprises:
a plurality of the cells arranged in an array.

6. The semiconductor device of claim 4 , wherein
the first to third wells, the first to fifth doped regions, and one sixth doped region in the plurality of sixth doped regions are configured in a first cell of a layout of the semiconductor device, and
the first to third wells, the first to fifth doped regions, and the plurality of sixth doped regions are configured in a second cell of the layout of the semiconductor device, and
the semiconductor device further comprises:
at least one of a plurality of the first cells and at least one of a plurality of the second cells arranged in an array.

7. The semiconductor device of claim 1 , further comprising:
a third well of the first type, disposed on the substrate and adjacent to the second well;
a fifth doped region of the first type, disposed in the third well, wherein the fifth doped region is configured as a first terminal of a third diode and is coupled to the first voltage terminal configured to receive the first supply voltage;
a sixth doped region of the second type, disposed in the third well, wherein the sixth doped region is configured as a second terminal of the third diode and is coupled to the first voltage terminal;
a fourth well of the second type, disposed on the substrate and adjacent to the third well;
a seventh doped region of the first type, disposed in the fourth well, wherein the seventh doped region is configured as a first terminal of a fourth diode and is coupled to the I/O pad; and
an eighth doped region of the second type, disposed in the fourth well, wherein the eighth doped region is configured as a second terminal of the fourth diode and is coupled to the second voltage terminal configured to receive the second supply voltage.

8. The semiconductor device of claim 7 , wherein the third doped region, the second well, the substrate, the third well, and the sixth doped region are configured as a third ESD path between the first voltage terminal and the second voltage terminal.

9. The semiconductor device of claim 7 , wherein the first to fourth wells and the first to eighth doped region are configured in a cell of a layout of the semiconductor device, and the semiconductor device further comprises:
a plurality of the cells arranged in an array.

10. A semiconductor device, comprising:
a substrate;
a first well of a first type disposed on the substrate;
a first doped region of the first type and a second doped region of a second type different from the first type that are disposed in the first well, wherein the first doped region is configured to be coupled to a first voltage terminal to receive a first supply voltage, and the second doped region is configured to be coupled to an input/output (I/O) pad;
a second well of the second type arranged adjacent to the first well and disposed on the substrate; and
a third doped region of the first type and a fourth doped region of the second type that are disposed in the second well, wherein the third doped region and the fourth doped region are configured to be coupled to a second voltage terminal to receive a second supply voltage different from the first supply voltage;
wherein the third doped region is disposed between the second doped region and the fourth doped region, and
the second doped region, the first well, the substrate, the second well, and the third doped region are configured to transmit an electrostatic discharge current flowing between the I/O pad and the second voltage terminal.

11. The semiconductor device of claim 10 , further comprising:
a shallow trench isolation region disposed sandwiched between the second doped region and the third doped region.

12. The semiconductor device of claim 10 , further comprising:
a third well of the first type, wherein the second well is arranged between the first well and the third well;
a fifth doped region of the first type and a sixth doped region of the second type that are disposed in the third well, wherein the fifth doped region and the sixth doped region are configured to be coupled to the first voltage terminal;
wherein the sixth doped region, the substrate, the third well, the second well, and the third doped region are configured to transmit an electrostatic discharge current flowing between the first voltage terminal and the second voltage terminal.

13. The semiconductor device of claim 10 , further comprising:
a third well of the second type, wherein the first well is disposed between the second well and the third well; and
a fifth doped region of the first type and a plurality of sixth doped regions that are disposed in the third well, wherein the fifth doped region

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Peng Po-Lin
• Chu Li-Wei
• Tsai Ming-Fu
• Lee Jam-Wem
• Su Yu-Ti

Classifications

• H10W42/80

  protecting against overcurrent or overload, e.g. fuses or shunts (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10W42/60

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10D89/911

  using passive elements as protective elements · CPC title

• H10D89/60

  Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] · CPC title

• H10D84/615

  Combinations of vertical BJTs and one or more of resistors or capacitors · CPC title