Device for generating verification vector for circuit design verification, circuit design system, and reinforcement learning method of the device and the circuit design system

Patent metadata

Field	Value
Publication number	US-11281832-B2
Application number	US-202016788924-A
Country	US
Kind code	B2
Filing date	Feb 12, 2020
Priority date	Feb 13, 2019
Publication date	Mar 22, 2022
Grant date	Mar 22, 2022

Abstract

A device for verifying a circuit design including a first circuit block and a second circuit block includes a verification vector generator and a design verifier. The verification vector generator determines a first verification vector by performing reinforcement learning through neural network computation based on a coverage corresponding to a first test vector, the coverage being determined based on a state transition of the first circuit block generated by inputting the first test vector to the first circuit block. The design verifier performs design verification for the first circuit block by using the first verification vector.

First claim

What is claimed is:

1. A device for verifying a circuit design comprising a first circuit block and a second circuit block, the device comprising:
a verification vector generator configured to determine a first verification vector by performing reinforcement learning through neural network computation based on a coverage corresponding to a first test vector, the coverage being determined based on a state transition of the first circuit block generated by inputting the first test vector to the first circuit block; and
a design verifier configured to perform design verification for the first circuit block by using the first verification vector,
wherein the verification vector generator is configured to obtain a reward according to a change of the coverage corresponding to the first test vector, and apply the obtained reward to the reinforcement learning.

2. The device of claim 1 , wherein the coverage corresponding to the first test vector corresponds to a coverage of a state transition history of the first circuit block in which the first test vector has been finally input to the first circuit block and accumulated through the reinforcement learning.

3. The device of claim 1 , wherein the verification vector generator is configured to compare the first test vector with a state transition history of the first circuit block that is accumulated through the reinforcement learning before the first test vector is input to the first circuit block, and
when a new state transition of the first circuit block has been generated by the first test vector, generate a first reward of a positive value and apply the generated first reward of the positive value to the reinforcement learning, and when the new state transition of the first circuit block has not been generated by the first test vector, generate a second reward of a negative value and apply the generated second reward of the negative value to the reinforcement learning.

4. The device of claim 1 , wherein the reward is obtained by using an approximate model that is generated through learning a trend of the state transition of the first circuit block according to all possible values of the first test vector based on a policy gradient algorithm.

5. The device of claim 1 , wherein the verification vector generator is configured to change the first test vector based on the reinforcement learning and perform the reinforcement learning based on a coverage corresponding to the changed first test vector.

6. The device of claim 5 , wherein the verification vector generator is configured to change a value of the first test vector or add at least one command to the first test vector to meet verification characteristics for a parameter generating the state transition of the first circuit block.

7. The device of claim 6 , wherein the circuit design corresponds to a dynamic random access memory (DRAM) circuit design, and the first circuit block is either a mode register set (MRS) block in which the state transition occurs due to an MRS-related parameter, or a command block in which the state transition occurs due to a command-related parameter.

8. The device of claim 1 , wherein the first test vector is compressed by a data lossless compression scheme.

9. The device of claim 1 , wherein, when the coverage corresponding to the first test vector is equal to or greater than a reference coverage, the verification vector generator is configured to determine the first test vector as the first verification vector.

10. The device of claim 1 , wherein, when the first circuit block is connected to the second circuit block, and first characteristics of a first parameter generating the state transition of the first circuit block are different from second characteristics of a second parameter generating the state transition of the second circuit block, the verification vector generator is configured to perform the reinforcement learning for determining a second verification vector corresponding to the second circuit block while the determined first verification vector is input to the first circuit block.

11. A device for verifying a circuit design comprising a first circuit block and a second circuit block, the device comprising:
a verification vector generator configured to determine a first verification vector by performing reinforcement learning through neural network computation based on a coverage corresponding to a first test vector, the coverage being determined based on a state transition of the first circuit block generated by inputting the first test vector to the first circuit block; and
a design verifier configured to perform design verification for the first circuit block by using the first verification vector,
wherein the first test vector comprises a plurality of commands, and the verification vector generator is configured to generate a reward for each command by back-tracking a state transition history of the first circuit block generated by inputting the first test vector and apply the generated reward to the reinforcement learning.

12. A device for verifying a circuit design comprising a first circuit block and a second circuit block, the device comprising:
a verification vector generator configured to determine a first verification vector by performing reinforcement learning through neural network computation based on a coverage corresponding to a first test vector, the coverage being determined based on a state transition of the first circuit block generated by inputting the first test vector to the first circuit block; and
a design verifier configured to perform design verification for the first circuit block by using the first verification vector,
wherein the verification vector generator is configured to add at least one command to the first test vector based on the reinforcement learning and to perform the reinforcement learning by inputting the added at least one command to the first circuit block.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Huh In
• Ko Jeong-Hoon
• Choi Hyo-Jin
• Kim Seung-Ju
• Jeong Chang-Wook
• Chai Joon-Wan
• Park Kwang-Il
• Park Youn-Sik
• Park Hyun-Sun
• Oh Young-Min
• Lee Jun-Haeng
• Lee Tae-Ho

Classifications

• G06N3/092

  Reinforcement learning · CPC title

• G06N3/09

  Supervised learning · CPC title

• G06N3/08 Primary

  Learning methods · CPC title

• G06F30/33 Primary

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F30/27

  using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model · CPC title