Image sensors and image processing systems using multilevel signaling techniques

Patent metadata

Field	Value
Publication number	US-11277579-B2
Application number	US-201916678384-A
Country	US
Kind code	B2
Filing date	Nov 8, 2019
Priority date	Jun 11, 2014
Publication date	Mar 15, 2022
Grant date	Mar 15, 2022

Abstract

An image sensor includes a pixel array configured to generate a plurality of pixel signals, an analog to digital converter circuit coupled to the pixel array and configured to generate respective digital codes responsive to respective ones of the pixel signals, a plurality of memories, respective ones of which are configured to store respective bits of the digital codes, a signal processing circuit coupled to a plurality of memories and configured to generate analog signals responsive to the stored bits, each of the analog signals corresponding to multiple ones of the stored bits, and a comparator circuit configured to compare the analog signals to respective ones of a plurality of reference signals to generate digital signals corresponding to the multiple ones of the stored bits. Related image processing systems and methods are also described.

First claim

What is claimed is:

1. An image sensor comprising:
a memory configured to store first digital signals generated based on pixel signals;
a signal generator configured to generate a first weighted sum signal and a second weighted sum signal responsive to N number of 1-bit signal among the first digital signals; and
a comparator configured to generate a second digital signal in response to the first weighted sum signal,
wherein the first weighted sum signal has one of levels of more than N different levels,
wherein N is a natural number,
wherein the signal generator is further configured to:
receive the N number of 1-bit signal among the first digital signals from the memory,
compare a first 1-bit signal received from a first address in the memory with a second first 1-bit signal received from a second address in the memory, and
generate the first weighted sum signal based on a result of the comparison between the first 1-bit signal and the second 1-bit signal.

2. The image sensor of claim 1 , the second weighted sum signal has one of the levels more than N different levels.

3. The image sensor of claim 1 , wherein each of the first and the second weighted sum signals has one of (N+1) different levels.

4. The image sensor of claim 1 , wherein the N is 2, and the N number of 1-bit signal includes a first 1-bit signal and a second 1-bit signal.

5. The image sensor of claim 4 , wherein the comparator is configured to generate the second digital signal corresponding to the first 1-bit signal and a third digital signal corresponding to the second 1-bit signal in response to the first weighted sum signal.

6. The image sensor of claim 4 , wherein the comparator is configured to generate the second digital signal corresponding to the first 1-bit signal and a third digital signal corresponding to the second 1-bit signal in response to a difference between the first weighted sum signal and the second weighted sum signal.

7. The image sensor of claim 4 , wherein the comparator is configured to generate the second digital signal corresponding to the first 1-bit signal and a third digital signal corresponding to the second 1-bit signal by comparing the first weighted sum signal to each of a plurality of reference signals.

8. The image sensor of claim 4 , wherein the comparator is configured to generate the second digital signal corresponding to the first 1-bit signal and a third digital signal corresponding to the second 1-bit signal by comparing a difference between the first weighted sum signal and the second weighted sum signal to each of a plurality of reference signals.

9. An image sensor comprising:
a pixel array;
an analog-to-digital converter configured to receive pixel signals from the pixel array and to generate a first 1-bit digital signal and a second 1-bit digital signal;
a memory configured to store the first 1-bit digital signal and the second 1-bit digital signal;
a signal processor configured to generate a first weighted signal in response to the first 1-bit digital signal and the second 1-bit digital signal, the first weighted signal having one of levels of more than two different levels;
a comparator configured to generate a first output signal in response to the first weighted signal and a first reference signal,
wherein the signal processor is further configured to:
receive the first 1-bit digital signal from a first address in the memory and the second 1-bit digital signal from a second address in the memory
compare the first 1-bit signal with the second first 1-bit signal, and
generate the first weighted sum signal based on a result of the comparison between the first 1-bit signal and the second 1-bit signal.

10. The image sensor of claim 9 , wherein the signal processor configured to generate a second weighted signal in response to the first 1-bit digital signal and the second 1-bit digital signal, the second weighted signal having one of the levels of more than two different levels.

11. The image sensor of claim 10 , wherein the signal processor configured to generate the second weighted signal in response to the first 1-bit digital signal and the second 1-bit digital signal, the second weighted signal having one of 3 different levels.

12. The image sensor of claim 9 , wherein the comparator configured to generate the first output signal in response to the first weighted signal and at least two different reference signals.

13. The image sensor of claim 9 , wherein the first and second 1-bit digital signals are generated based on the same pixel in the pixel array.

14. The image sensor of claim 9 , wherein the first 1-bit digital signal is generated based on a first pixel in the pixel array and the second 1-bit digital signal is generated based on a second pixel in the pixel array, and
wherein the first pixel is different from the second pixel.

15. The image sensor of claim 1 , wherein the signal generator generates the first weighted sum signal by combining the N number of 1-bit signal among the first digital signals.

16. The image sensor of claim 9 , wherein the signal generator generates the first weighted sum signal by combining the first 1-bit digital signal and the second 1-bit digital signal.

17. An image sensor comprising:
a memory configured to store first digital signals generated based on pixel signals;
a signal generator configured to generate a weighted sum signal based on N number of 1-bit signal among the first digital signals stored in the memory;
a comparator configured to generate a second digital signal in response to the weighted sum signal,
wherein the weighted sum signal has one of levels of more than N different levels, and wherein N is a natural number,
wherein the signal generator is further configured to:
receive the N number of 1-bit signal among the first digital signals from the memory,
compare a first 1-bit signal received from a first address in the memory with a second first 1-bit signal received from a second address in the memory, and
generate the weighted sum signal based on a result of the comparison between the first 1-bit signal and the second 1-bit signal.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoo Kwi Sung
• Jin Eun Young

Classifications

• H04N23/76 Primary

  by influencing the image signals · CPC title

• H04N25/78 Primary

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H04N25/779 Primary

  Circuitry for scanning or addressing the pixel array · CPC title

• H04N5/37455 Primary

  Electricity · mapped topic

• H04N5/378

  Electricity · mapped topic