Full-bridge inverter with unipolar switching scheme and its method of operation

Patent metadata

Field	Value
Publication number	US-11277078-B2
Application number	US-202017080194-A
Country	US
Kind code	B2
Filing date	Oct 26, 2020
Priority date	Oct 25, 2019
Publication date	Mar 15, 2022
Grant date	Mar 15, 2022

Abstract

A full-bridge inverter based on a unipolar switching scheme includes a first branch and a second branch in parallel between a first DC node and a second node, the first branch including a first higher switch and a first lower switch in series, and the second branch including a second higher switch and a second lower switch in series. A filter circuit includes a first inductor and a second inductor. One pin of the first inductor is coupled with a first branch conductor, and the first branch conductor is coupled between the first higher switch and the first lower switch, and an opposite pin of the first inductor is electrically coupled with a first output node. One pin of the second inductor is coupled with a second branch conductor, the second branch conductor is coupled between the second higher switch and the second lower switch, and an opposite pin of the second inductor is coupled with a second output node of the full-bridge inverter. A first filtering unit switch, a first filter diode, a second filter diode and a second filtering unit switch in series are coupled between the first branch conductor and the second branch conductor, cathodes of the first diode and the second diode are coupled together. A cathode of a third filter diode is coupled with the first output node, and a cathode of a fourth filter diode is coupled with the second output node. The anodes of the third diode and the fourth diode are coupled together. A third inductor is coupled between the cathodes of the first diode and the second diode and the anodes of the third diode and the fourth diode.

First claim

The invention claimed is:

1. A full-bridge inverter based on a unipolar switching scheme, the full-bridge inverter being configured to convert DC electric power to AC electric power, wherein the full-bridge inverter comprises
a first branch and a second branch, which are electrically coupled in parallel between a first DC node and a second DC node of the full-bridge inverter configured to receive the DC electric power, the first branch comprising a first higher switch and a first lower switch in series, and the second branch comprising a second higher switch and a second lower switch in series;
a filter circuit comprising
a first inductor, one pin of the first inductor being electrically coupled with a first branch conductor, the first branch conductor being electrically coupled between the first higher switch and the first lower switch, and an opposite pin of the first inductor being electrically coupled with a first output node of the full-bridge inverter;
a second inductor, one pin of the second inductor being electrically coupled with a second branch conductor, the second branch conductor being electrically coupled between the second higher switch and the second lower switch, and an opposite pin of the second inductor being electrically coupled with a second output node of the full-bridge inverter;
a first filtering unit switch, a first filter diode, a second filter diode and a second filtering unit switch in series electrically coupled between the first branch conductor and the second branch conductor, cathodes of the first diode and the second diode being electrically coupled together;
a third filter diode, whose cathode is electrically coupled with the first output node, and a fourth filter diode, whose cathode is electrically coupled with the second output node, the anodes of the third diode and the fourth diode being electrically coupled together; and
a third inductor electrically coupled between the cathodes of the first diode and the second diode and the anodes of the third diode and the fourth diode.

2. The full-bridge inverter of claim 1 , which further comprises electric path circuits configured to conduct an electric current between the third inductor and the first DC node in response to switching the first filtering unit switch in an electrically conducting state, and conduct an electric current between the third inductor and the second DC node in response to switching the second filtering unit switch in an electrically conducting state.

3. The full-bridge inverter of claim 2 , wherein the electric path circuits comprise a first electric path circuit electrically coupled between the second output node and the lower node for conducting an electric current between the third inductor and the second DC node, and a second electric path circuit electrically coupled between the first output node and the first DC node for conducting an electric current between the third inductor and the first DC node.

4. The full-bridge inverter of claim 2 , wherein the first electric path circuit comprises a first path switch and a first capacitor in series, the first path switch being configured to switch in an electrically conducting state for conducting an electric current between the third inductor and the first DC node, and the second electric path circuit comprises a second path switch and a second capacitor in series, the second path switch being configured to switch in an electrically conducting state for conducting an electric current between the third inductor and the second DC node.

5. The full-bridge inverter of claim 1 , wherein the first higher switch, and the second higher switch comprises a bipolar junction transistor and a reverse biased diode; and the first lower switch and the second lower switch comprises a field effect transistor and a reverse biased diode.

6. A method of operation of a full-bridge inverter based on a unipolar switching scheme, the method comprising filtering a signal within the full-bridge inverter with a first inductor, a second inductor, and third inductor, where
one pin of the first inductor being electrically coupled with a first branch conductor, the first branch conductor being electrically coupled between the first higher switch and the first lower switch, and an opposite pin of the first inductor being electrically coupled with a first output node of the full-bridge inverter;
one pin of the second inductor being electrically coupled with a second branch conductor, the second branch conductor being electrically coupled between the second higher switch and the second lower switch, and an opposite pin of the second inductor being electrically coupled with a second output node of the full-bridge inverter;
the third inductor being electrically coupled between cathodes of a first diode and a second diode and a anodes of a third diode and a fourth diode, where the first filter diode, the second filter diode and a second filtering unit switch in series are electrically coupled between the first branch conductor and the second branch conductor, cathodes of the first diode and the second diode are electrically coupled together, and a cathode of the third diode being electrically coupled with a first output and a cathode of the fourth diode being electrically coupled with a second output of the full-bridge inverter.

7. The method of claim 6 , further comprising conducting, through electric path circuits, an electric current between the third inductor and the first DC node in response to switching the first filtering unit switch into an electrically conducting state, and an electric current between the third inductor and the second DC node in response to switching the second filtering unit switch into an electrically conducting state.

8. The method of claim 6 , the method further causing the full-bridge inverter to go through the following succeeding operational states in cycles:
a first stage where a first higher switch is in electrically conducting state, the second lower switch and a first filtering unit switch are in an electrically non-conducting state;
a second stage where the first filtering unit switch is in an electrically conducting state causing an electric current flowing through a third inductor to increase until it reaches a same strength as an electric current flowing through a first inductor;
a third stage where a reverse diode of a second higher switch is in an electrically non-conducting state, while capacitance of a second higher switch is discharging, and capacitance of a second lower switch is charging;
a fourth stage where a voltage over the second lower switch is zero and a reverse diode parallel to the second lower switch conducts electrically, the second lower switch switches into an electrically conducting state before an electric current flowing through the reverse diode parallel to the second lower switch becomes zero, the third inductor resets and a the first filtering unit switch is switched into an electrically non-conductive state when an electric current flowing through the third inductor is zero;
a fifth stage, whose duration depends on a duty cycle of a resonance between an inductance of the third inductor, and the capacitances of the second higher switch and a second lower switch;
a sixth stage where the second lower switch is in an electrically non-conducting state under a zero-voltage condition, and which ends when a voltage of the second lower switch equals the input voltage of the full-bridge inverter.

9. The method of claim 6 , wherein
in a first stage, switching a first higher switch of a first branch in an electrically conducting state, while a second electric path circuit is in an electrically conducting state, for suppressing differential mode ripple and providing

Assignees

• Abb Schweiz Ag

Inventors

• Bianda Enea
• Li Tin-Ho
• Huusari Juha
• Ho Ngai-Man

Classifications

• H02M1/34

  Snubber circuits · CPC title

• H02M1/44

  Circuits or arrangements for compensating for electromagnetic interference in converters or inverters · CPC title

• H02M1/14

  Arrangements for reducing ripples from DC input or output · CPC title

• Y02B70/10

  Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title

• H02M7/5387 Primary

  in a bridge configuration · CPC title