Programmable multi-stage driver system

Patent metadata

Field	Value
Publication number	US-11277005-B2
Application number	US-202117171301-A
Country	US
Kind code	B2
Filing date	Feb 9, 2021
Priority date	Feb 20, 2020
Publication date	Mar 15, 2022
Grant date	Mar 15, 2022

Abstract

A multi-stage driver system includes a switched mode power circuit for providing a direct current (DC) power signal to an electrical load and a control block. Control block includes interfaces coupled to receive at least one real-time input signal from a high voltage region or a low voltage region of the switched mode power circuit and to provide at least one control signal to the high voltage region or the low voltage region. Control block configures the switched mode power circuit to provide the DC power signal having at least one power parameter within a tolerance of a power configuration setting value of the electrical load. Control block responds to the at least one real-time input signal from the high voltage region or the low voltage region to adjust operation of the high voltage region or the low voltage region via the at least one control signal.

First claim

The invention claimed is:

1. A multi-stage driver system comprising:
a switched mode power circuit for providing a direct current (DC) power signal to an electrical load, the switched mode power circuit including a high voltage region, a low voltage region, and an isolation barrier coupled between the high voltage region and the low voltage region; and
a control block coupled to control operations of the switched mode power circuit and including at least one microcontroller having a processor, a memory, and interfaces coupled to the high voltage region and the low voltage region, wherein:
the interfaces are coupled to receive at least one real-time input signal from the high voltage region or the low voltage region and to provide at least one control signal to the high voltage region or the low voltage region;
the at least one microcontroller includes programming stored in the memory for execution by the processor, wherein execution of the programming by the processor configures the multi-stage driver system to implement functions, including functions to control operation of the high voltage region or the low voltage region to:
configure the switched mode power circuit to provide the DC power signal having at least one power parameter within a tolerance of a power configuration setting value of the electrical load; and
respond to the at least one real-time input signal from the high voltage region or the low voltage region to adjust operation of the high voltage region or the low voltage region via the at least one control signal.

2. The multi-stage driver system of claim 1 , wherein:
the interfaces are coupled to receive the at least one real-time input signal from the high voltage region; and
execution of the programming by the processor configures the multi-stage driver system to implement functions, including functions to control operation of the high voltage region to respond to the at least one real-time input signal from the high voltage region to adjust operation of the high voltage region via the at least one control signal.

3. The multi-stage driver system of claim 1 , wherein:
the interfaces are coupled to receive the at least one real-time input signal from the low voltage region; and
execution of the programming by the processor configures the multi-stage driver system to implement functions, including functions to control operation of the high voltage region to respond to the at least one real-time input signal from the low voltage region to adjust operation of the high voltage region via the at least one control signal.

4. The multi-stage driver system of claim 1 , wherein:
the interfaces are coupled to receive the at least one real-time input signal from the high voltage region; and
execution of the programming by the processor configures the multi-stage driver system to implement functions, including functions to control operation of the low voltage region to respond to the at least one real-time input signal from the high voltage region to adjust operation of the low voltage region via the at least one control signal.

5. The multi-stage driver system of claim 1 , wherein:
the interfaces are coupled to receive the at least one real-time input signal from the low voltage region; and
execution of the programming by the processor configures the multi-stage driver system to implement functions, including functions to control operation of the low voltage region to respond to the at least one real-time input signal from the low voltage region to adjust operation of the low voltage region via the at least one control signal.

6. The multi-stage driver system of claim 1 , wherein the at least one power parameter or the power configuration setting value corresponds to at least one of a voltage (V), a current (amperes), a constant voltage configuration, a constant current configuration, or a modulation scheme of the high voltage region or the low voltage region.

7. The multi-stage driver system of claim 1 , wherein:
the function to respond to the at least one real-time input signal from the high voltage region or the low voltage region to adjust operation of the high voltage region or the low voltage region via the at least one control signal includes:
optimizing performance of the switched mode power circuit while maintaining the at least one power parameter of the DC power signal within the tolerance of the power configuration setting value of the electrical load.

8. The multi-stage driver system of claim 7 , wherein:
the at least one real-time input signal includes a reading of an AC input signal;
the at least one control signal includes a pulse width modulation (PWM) gate drive output; and
the function of optimizing performance of the switched mode power circuit while maintaining the at least one power parameter of the DC power signal within the tolerance of the power configuration setting value of the electrical load includes:
based on the AC input signal reading, controlling the PWM gate drive output to at least two wide-bandgap FETs of the high voltage region to efficiently tune a bus voltage of a high voltage DC bus of the high voltage region.

9. The multi-stage driver system of claim 7 , wherein:
the at least one real-time input signal includes a reading of output current to the electrical load from a switched converter circuit of the low voltage region;
the at least one control signal includes a pulse width modulation (PWM) gate drive output; and
the function of optimizing performance of the switched mode power circuit while maintaining the at least one power parameter of the DC power signal within the tolerance of the power configuration setting value of the electrical load includes:
based on the electric load output current reading, controlling the PWM gate drive output to at least two wide-bandgap FETs of the low voltage region to maintain a constant current configuration.

10. The multi-stage driver system of claim 7 , wherein:
the at least one real-time input signal includes a reading of output voltage to the electrical load from a switched converter circuit of the low voltage region;
the at least one control signal includes a pulse width modulation (PWM) gate drive output; and
the function of optimizing performance of the switched mode power circuit while maintaining the at least one power parameter of the DC power signal within the tolerance of the power configuration setting value of the electrical load includes:
based on the electric load output voltage reading, controlling the PWM gate drive output to at least two wide-bandgap FETs of the low voltage region to maintain a constant voltage configuration.

11. The multi-stage driver system of claim 7 , wherein:
the at least one real-time input signal includes a reading of a bus voltage of a low voltage DC bus of the low voltage region;
the at least one control signal includes a pulse width modulation (PWM) gate drive output; and
the function of optimizing performance of the switched mode power circuit while maintaining the at least one power parameter of the DC power signal within the tolerance of the power configuration setting value of the electrical load includes:
based on the reading of the bus voltage reading, controlling the PWM gate drive output to at least two wide-bandgap FETs of the high voltage region to efficiently tune a high voltage signal of the high voltage region.

12. The multi-stage driver system of claim 7 , wherein:
the at least one real-time input signal includes a reading of input current to a switched converter circuit of the low voltage region;
the at least one control signal includes a pulse width modulation (PWM) gate drive outpu

Assignees

• Abl Ip Holding Llc

Inventors

• White Sean P
• Malone Gregory
• Aggarwal Januk
• Ramer David P

Classifications

• H02J13/1335

  involving a local wireless network, e.g. Wi-Fi®, ZigBee® or Bluetooth® · CPC title

• H02J1/106

  for load balancing, symmetrisation, or sharing · CPC title

• H02J1/082 Primary

  DC supplies with two or more different DC voltage levels · CPC title

• H02J1/14 Primary

  Balancing load and power generation in DC networks · CPC title

• H05B45/3725

  Switched mode power supply [SMPS] · CPC title