Semiconductor device, inverter circuit, driving device, vehicle, and elevator

Patent metadata

Field	Value
Publication number	US-11276751-B2
Application number	US-202016797037-A
Country	US
Kind code	B2
Filing date	Feb 21, 2020
Priority date	Aug 7, 2019
Publication date	Mar 15, 2022
Grant date	Mar 15, 2022

Abstract

A semiconductor device of an embodiment includes a silicon carbide layer having first and second plane, the silicon carbide layer including trench having a first portion and a second portion, the second portion having a width smaller than the first portion, an n-type first silicon carbide region, a p-type second silicon carbide region between the first silicon carbide region and the first plane, a p-type third silicon carbide region between the second silicon carbide region and the first plane and having a p-type impurity concentration lower than the second silicon carbide region, an n-type fourth silicon carbide region between the third silicon carbide region and the first plane, and an n-type fifth silicon carbide region between the second portion and the second silicon carbide region and having an n-type impurity concentration higher than the first silicon carbide region; and a gate electrode in the trench.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first electrode;
a second electrode;
a silicon carbide layer located between the first electrode and the second electrode, the silicon carbide layer having a first plane parallel to a first direction and a second direction intersecting the first direction, and a second plane parallel to the first direction and the second direction, the second plane facing the first plane, the silicon carbide layer including
a trench located on a first plane side, the trench extending in the first direction on the first plane, the trench having a first portion and a second portion closer to the second plane than the first portion, the second portion having a width in the second direction smaller than a width of the first portion in the second direction,
a first silicon carbide region of n-type,
a second silicon carbide region of p-type located between the first silicon carbide region and the first plane,
a third silicon carbide region of p-type located between the second silicon carbide region and the first plane, the third silicon carbide region having a p-type impurity concentration lower than a p-type impurity concentration of the second silicon carbide region,
an fourth silicon carbide region of n-type located between the third silicon carbide region and the first plane, and
an fifth silicon carbide region of n-type located between the second portion and the second silicon carbide region, the fifth silicon carbide region having an n-type impurity concentration higher than an n-type impurity concentration of the first silicon carbide region;

a gate electrode located in the trench; and
a gate insulating layer located between the gate electrode and the silicon carbide layer,
wherein the fifth silicon carbide region is in physical contact with the first silicon carbide region on a line extending in a third direction perpendicular to the first direction and the second direction from the second portion to the second plane.

2. The semiconductor device according to claim 1 , wherein a p-type impurity concentration of the fifth silicon carbide region is higher than a p-type impurity concentration of the first silicon carbide region.

3. The semiconductor device according to claim 2 , wherein the fifth silicon carbide region has an n-type impurity concentration and a p-type impurity concentration of 1×10 18 cm −3 or more.

4. The semiconductor device according to claim 1 , wherein a thickness of the fifth silicon carbide region in the second direction is 0.01 μm or more and 0.2 μm or less.

5. The semiconductor device according to claim 1 , wherein a p-type impurity concentration of the second silicon carbide region is 10 or more times a p-type impurity concentration of the third silicon carbide region.

6. The semiconductor device according to claim 1 , wherein a distance from the second plane to the trench is shorter than a distance from the second plane to the third silicon carbide region.

7. The semiconductor device according to claim 1 , wherein a distance from the second plane to the trench is longer than a distance from the second plane to the second silicon carbide region.

8. The semiconductor device according to claim 1 , wherein a distance from the second plane to the first portion is longer than a distance from the second plane to the third silicon carbide region, and the distance from the second plane to the first portion is shorter than a distance from the second plane to the fourth silicon carbide region.

9. The semiconductor device according to claim 1 , wherein a distance from the first plane to the fifth silicon carbide region is shorter than a distance from the first plane to the second silicon carbide region.

10. The semiconductor device according to claim 1 , wherein a shortest distance from the second plane to the fifth silicon carbide region is shorter than a shortest distance from the second plane to the second silicon carbide region.

11. The semiconductor device according to claim 1 , wherein the silicon carbide layer further includes a sixth silicon carbide region located between the trench and the first silicon carbide region, the sixth silicon carbide region having an n-type impurity concentration higher than an n-type impurity concentration of the fifth silicon carbide region.

12. The semiconductor device according to claim 11 , wherein a distance from the second plane to the sixth silicon carbide region is shorter than a distance from the second plane to the fifth silicon carbide region.

13. The semiconductor device according to claim 11 , wherein a width of the sixth silicon carbide region in the second direction is smaller than a width of the fifth silicon carbide region in the second direction.

14. The semiconductor device according to claim 1 , wherein the silicon carbide layer further includes a seventh silicon carbide region located between the third silicon carbide region and the first plane, the seventh silicon carbide region having a p-type impurity concentration higher than a p-type impurity concentration of the third silicon carbide region.

15. The semiconductor device according to claim 14 , wherein the seventh silicon carbide region is repeatedly disposed on the first plane in the first direction with the fourth silicon carbide region interposed between the seventh silicon carbide regions.

16. An inverter circuit comprising the semiconductor device according to claim 1 .

17. A drive device comprising the semiconductor device according to claim 1 .

18. A vehicle comprising the semiconductor device according to claim 1 .

19. An elevator comprising the semiconductor device according to claim 1 .

20. A semiconductor device comprising:
a first electrode;
a second electrode;
a silicon carbide layer located between the first electrode and the second electrode, the silicon carbide layer having a first plane parallel to a first direction and a second direction intersecting the first direction, and a second plane parallel to the first direction and the second direction, the second plane facing the first plane, the silicon carbide layer including
a trench located on a first plane side, the trench extending in the first direction on the first plane, the trench having a first portion and a second portion closer to the second plane than the first portion, the second portion having a width in the second direction smaller than a width of the first portion in the second direction,
a first silicon carbide region of n-type,
a second silicon carbide region of p-type located between the first silicon carbide region and the first plane,
a third silicon carbide region of p-type located between the second silicon carbide region and the first plane, the third silicon carbide region having a p-type impurity concentration lower than a p-type impurity concentration of the second silicon carbide region,
an fourth silicon carbide region of n-type located between the third silicon carbide region and the first plane, and
an fifth silicon carbide region of n-type located between the second portion and the second silicon carbide region, the fifth silicon carbide region having an n-type impurity concentration higher than an n-type impurity concentration of the first silicon carbide region;

a gate electrode located in the trench; and
a gate insulating layer located between the gate electrode and the silicon carbide layer,
wherein a shortest distance from the second plane to the fifth silicon carbide region is shorter than a shortest distance from the secon

Assignees

• Toshiba Kk

Inventors

• Kyogoku Shinya
• Oshima Toshiyuki
• Iijima Ryosuke

Classifications

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10P30/22

  using masks · CPC title

• H10D64/01366

  the semiconductor being silicon carbide · CPC title

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title

• H10D62/8325

  Silicon carbide · CPC title