Integrated semiconductor device and electronic apparatus

Patent metadata

Field	Value
Publication number	US-11276690-B2
Application number	US-201816755817-A
Country	US
Kind code	B2
Filing date	Nov 21, 2018
Priority date	Dec 28, 2017
Publication date	Mar 15, 2022
Grant date	Mar 15, 2022

Abstract

The present application provides an integrated semiconductor device and an electronic apparatus, comprising a semiconductor substrate and a first doped epitaxial layer having a first region, a second region, and a third region; a partition structure is arranged in the third region; the first region is formed having at least two second doped deep wells, and the second region is formed having at least two second doped deep wells; a dielectric island partially covers a region between two adjacent doped deep wells in the first region and second region; a gate structure covers the dielectric island; a first doped source region is located on the two sides of the gate structure, and a first doped source region located in the same second doped deep well is separated; a first doped trench is located on the two sides of the dielectric island in the first region, and extends laterally to the first doped source region.

First claim

What is claimed is:

1. An integrated semiconductor device, comprising:
a semiconductor substrate;
a first dopant type epitaxial layer located on a front side of the semiconductor substrate and comprising a first region, a second region, and a third region, wherein an isolation structure is provided in the third region;
second dopant type deep wells located in the first dopant type epitaxial layer, comprising at least two second dopant type deep wells located in the first region and at least two second dopant type deep wells located in the second region;
dielectric islands located on the first dopant type epitaxial layer, a part of the dielectric islands covering a region between two adjacent second dopant type deep wells in the first region, a part of the dielectric islands covering a region between two adjacent second dopant type deep wells in the second region, and the dielectric islands being not in contact with the adjacent second dopant type deep wells;
gate structures located on the first dopant type epitaxial layer and covering the dielectric islands and a part of regions of the second dopant type deep wells on both sides of the dielectric island;
first dopant type source regions located in the second dopant type deep wells below both sides of the gate structures, and the first dopant type source regions in the same second dopant type deep well being separated by a part of a region of a second dopant type source region; and
first dopant type trenches located on both sides of the part of the dielectric islands located in the first region, and in the first dopant type epitaxial layer, the first dopant type trenches extending laterally to the first dopant type source regions;
wherein the first dopant type is opposite to the second dopant type;
wherein the isolation structure comprises at least one of the second dopant type deep wells located in the third region and a field oxygen covering the second dopant type deep well in the third region.

2. The integrated semiconductor device according to claim 1 , wherein the dielectric island has a thickness ranging from 5000 Å to 10000 Å.

3. The integrated semiconductor device according to claim 1 , wherein the dielectric island has a length ranging from 2 μm to 5 μm.

4. The integrated semiconductor device according to claim 1 , wherein the isolation structure comprises at least one trench and the dielectric island covering the trench, and the trench is filled with a dielectric material layer.

5. The integrated semiconductor device according to claim 4 , wherein a depth of the trench is equal to or greater than a thickness of the first dopant type epitaxial layer.

6. The integrated semiconductor device according to claim 4 , wherein a width of the trench is 0.5 μm to 2 μm.

7. The integrated semiconductor device according to claim 4 , wherein the dielectric island and the trench are filled with thermal silicon oxide.

8. The integrated semiconductor device according to claim 1 , wherein the gate structure comprises a gate dielectric layer and a gate material layer.

9. The integrated semiconductor device according to claim 8 , wherein the gate dielectric layer is of a silicon dioxide material and the gate material layer is of polycrystalline silicon material.

10. The integrated semiconductor device according to claim 8 , wherein the gate dielectric layer has a thickness ranging from 500 Å to 1500 Å and the gate material layer has a thickness ranging from 2000 Ř10000 Å.

11. The integrated semiconductor device according to claim 1 , further comprising a drain formed on a rear side of the semiconductor substrate.

12. The integrated semiconductor device according to claim 1 , wherein the first dopant type epitaxial layer has a thickness of 45 μm to 65 μm and a resistivity of 15Ω·cm to 25Ω·cm.

13. The integrated semiconductor device according to claim 1 , wherein the semiconductor substrate is a semiconductor substrate of a first dopant type, the integrated semiconductor device comprises a VDMOS device comprising a depletion VDMOS device located in the first region and an enhanced VDMOS device located in the second region.

14. The integrated semiconductor device according to
claim 1 , wherein the semiconductor substrate is a semiconductor substrate of a second dopant type, the integrated semiconductor device comprises an IGBT device comprising a depletion IGBT device located in the first region and an enhanced IGBT device located in the second region.

15. An electronic apparatus comprising the integrated semiconductor device according to claim 1 .

16. An integrated semiconductor device, comprising:
a semiconductor substrate;
a first dopant type epitaxial layer located on a front side of the semiconductor substrate and comprising a first region, a second region, and a third region, wherein an isolation structure is provided in the third region;
second dopant type deep wells located in the first dopant type epitaxial layer, comprising at least two second dopant type deep wells located in the first region and at least two second dopant type deep wells located in the second region;
dielectric islands located on the first dopant type epitaxial layer, a part of the dielectric islands covering a region between two adjacent second dopant type deep wells in the first region, a part of the dielectric islands covering a region between two adjacent second dopant type deep wells in the second region, and the dielectric islands being not in contact with the adjacent second dopant type deep wells;
gate structures located on the first dopant type epitaxial layer and covering the dielectric islands and a part of regions of the second dopant type deep wells on both sides of the dielectric island;
first dopant type source regions located in the second dopant type deep wells below both sides of the gate structures, and the first dopant type source regions in the same second dopant type deep well; and
first dopant type trenches located on both sides of the part of the dielectric islands located in the first region, and in the first dopant type epitaxial layer, the first dopant type trenches extending laterally to the first dopant type source regions;
wherein the first dopant type is opposite to the second dopant type;
second dopant type source regions in the second dopant type deep wells in the first region and the second region, wherein the second dopant type source regions are located between the first dopant type source regions and in contact with the first dopant type source regions.

17. The integrated semiconductor device according to claim 16 , further comprising second dopant type well regions in the second dopant type deep wells in the first region and the second region, wherein the second dopant type well regions are located below the first dopant type source regions and the second dopant type source regions.

18. An integrated semiconductor device, comprising:
a semiconductor substrate;
a first dopant type epitaxial layer located on a front side of the semiconductor substrate and comprising a first region, a second region, and a third region, wherein an isolation structure is provided in the third region;
second dopant type deep wells located in the first dopant type epitaxial layer, comprising at least two second dopant type deep wells located in the first region and at least two second dopant type deep wells located in the second region;
dielectric islands located on the first dopant type epitaxial layer, a part of the dielectric islands covering a region between two adjacent second dopant type deep wells in th

Assignees

• Csmc Technologies Fab2 Co Ltd

Inventors

• Cheng Shikang
• Gu Yan
• Zhang Sen

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D30/66

  Vertical DMOS [VDMOS] FETs · CPC title

• H10D30/635

  having no inversion channels, e.g. vertical accumulation channel FETs [ACCUFET] or normally-on vertical IGFETs · CPC title

• H10D12/00

  Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT] · CPC title