Semiconductor device, switching power supply control IC, and switching power supply device

Patent metadata

Field	Value
Publication number	US-11276683-B2
Application number	US-201514792234-A
Country	US
Kind code	B2
Filing date	Jul 6, 2015
Priority date	Jun 20, 2013
Publication date	Mar 15, 2022
Grant date	Mar 15, 2022

Abstract

A semiconductor device has a configuration wherein a resistor that restricts overvoltage is inserted between an input terminal and the drain of JFETs, and the resistor is disposed on the JFETs. Also, the resistor is formed contiguously and integrally with a spiral form high breakdown voltage high resistance element that configures a resistive voltage divider circuit.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a lateral junction field effect transistor formed in an upper portion of a semiconductor substrate;
a dielectric provided on the junction field effect transistor;
relay wiring, provided inside the dielectric, and a pad, provided on the dielectric, electrically connected to the relay wiring, to which voltage is applied from the exterior; and
a first resistor element, electrically connected between, and in contact with, the drain of the junction field effect transistor and the relay wiring, respectively, provided inside the dielectric on the junction field effect transistor,
wherein an outer peripheral edge of the first resistor element that is provided inside the dielectric on the junction field effect transistor is disposed closer to an inner edge of the semiconductor device than is an outer peripheral edge of the pad,
wherein the pad provided on the dielectric extends to the inner edge of the semiconductor device, and
wherein no other pad is disposed between the outer peripheral edge of the pad and an inner edge of the drain.

2. The semiconductor device according to claim 1 , comprising
a second resistor element and third resistor element configuring a resistive voltage dividing circuit inside the dielectric; and
a planar form wherein the first resistor element, second resistor element, and third resistor element are formed contiguously in the order of the first resistor element, second resistor element, and third resistor element from the inner side is a spiral form.

3. The semiconductor device according to claim 1 , wherein the semiconductor device is formed on an IC chip.

4. A switching power supply device comprising:
the semiconductor device according to claim 1 ; and
a starting circuit connected to the semiconductor device.

5. The semiconductor device according to claim 1 , wherein a resistance value of the first resistance element is less than or equal to 200 ohms.

6. A semiconductor device, comprising:
a second conductivity type drift region formed in an upper portion of a first conductivity type semiconductor substrate;
a drain electrode connected to the drift region;
a second conductivity type source region provided in contact with the drift region in an upper portion of the semiconductor substrate around the drift region;
a first conductivity type gate region disposed in contact with the drift region in an upper portion of the semiconductor substrate;
a dielectric formed on the surface of the drift region;
a gate electrode connected to the gate region;
a source electrode connected to the source region;
relay wiring, provided inside the dielectric, and a pad, provided on the dielectric, electrically connected to the relay wiring, to which voltage is applied from the exterior; and
a first resistor element, electrically connected between, and in contact with, the drain electrode and the relay wiring, respectively, embedded inside the dielectric on the drift region,
wherein an outer peripheral edge of the first resistor element that is provided inside the dielectric on the junction field effect transistor is disposed closer to an inner edge of the semiconductor device than is an outer peripheral edge of the pad,
wherein the pad provided on the dielectric extends to the inner edge of the semiconductor device, and
wherein no other pad is disposed between the outer peripheral edge of the pad and an inner edge of the drain.

7. The semiconductor device according to claim 6 , comprising a second resistor element configuring a resistive voltage dividing circuit embedded inside the dielectric, wherein
one end of the second resistor element is electrically connected to the relay wiring.

8. The semiconductor device according to claim 7 , further comprising a third resistor element configuring the resistive voltage dividing circuit embedded inside the dielectric and, one end of the third resistor element being connected to the other end of the second resistor element, comprising intermediate tap wiring connected to the connection place.

9. The semiconductor device according to claim 8 , wherein
the planar form of the second resistor element and third resistor element is a spiral form wherein the second resistor element and third resistor element are formed contiguously in order from the inner side.

10. The semiconductor device according to claim 8 , wherein
the planar form of the first resistor element, second resistor element, and third resistor element is a spiral form wherein the first resistor element, second resistor element, and third resistor element are formed contiguously in order from the inner side.

11. The semiconductor device according to claim 6 , further comprising a second resistor element configuring a resistive voltage dividing circuit embedded inside the dielectric, wherein
one end of the second resistor element is electrically connected to the drain electrode.

12. The semiconductor device according to claim 11 , further comprising a third resistor element configuring the resistive voltage dividing circuit embedded inside the dielectric and, one end of the third resistor element being connected to the other end of the second resistor element, comprising intermediate tap wiring connected to the connection place.

13. The semiconductor device according to claim 12 , wherein
the planar form of the second resistor element and third resistor element is a spiral form wherein the second resistor element and third resistor element are formed contiguously in order from the inner side.

14. The semiconductor device according to claim 12 , wherein
the planar form of the first resistor element, second resistor element, and third resistor element is a spiral form wherein the first resistor element, second resistor element, and third resistor element are formed contiguously in order from the inner side.

15. The semiconductor device according to claim 6 , further comprising a second conductivity type drain region, of an impurity concentration higher than that of the drift region, formed in a surface layer of the semiconductor substrate in a region sandwiched between the drift region and drain electrode.

16. The semiconductor device according to claim 6 , further comprising:
a first source electrode connected to one portion of the source region; and
a second source electrode connected to the remaining portion of the source region.

17. The semiconductor device according to claim 6 , wherein
a plurality of the source region are formed around the drift region, and the gate region is formed in contact with the plurality of source regions and the drift region so as to surround the plurality of source regions and the drift region.

18. A semiconductor device, comprising:
a lateral junction field effect transistor formed in an upper portion of a semiconductor substrate;
a dielectric provided on the junction field effect transistor;
relay wiring, provided inside the dielectric, and a pad, provided on the dielectric, electrically connected to the relay wiring, to which voltage is applied from the exterior; and
a first resistor element, electrically connected between, and in contact with, the drain of the junction field effect transistor and the relay wiring, respectively, provided inside the dielectric on the junction field effect transistor,
wherein an outer peripheral edge of the first resistor element that is provided inside the dielectric on the junction field effect transistor is disposed closer to an inner edge of the semiconductor device than is an ou

Assignees

• Fuji Electric Co Ltd

Inventors

• Saito Masaru

Classifications

• H10D84/817

  Combinations of field-effect devices and resistors only · CPC title

• H10D84/00 Primary

  Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers · CPC title

• H10D84/87

  of PN-junction gate FETs · CPC title

• H10D64/111

  Field plates · CPC title

• H10D62/126

  Top-view geometrical layouts of the regions or the junctions · CPC title