Information processing apparatus, ising device, and control method for information processing apparatus

Patent metadata

Field	Value
Publication number	US-11275995-B2
Application number	US-201715609767-A
Country	US
Kind code	B2
Filing date	May 31, 2017
Priority date	Jul 13, 2016
Publication date	Mar 15, 2022
Grant date	Mar 15, 2022

Abstract

An individual ising device connected to common buses includes neuron circuits, a memory, and a router. The memory holds connection destination information per neuron circuit. An individual item of connection destination information includes first address information identifying one of a plurality of connection destination neuron circuits of a neuron circuit and second address information identifying a first ising device including at least one of the connection destination neuron circuits, the first and second address information being correlated. The router supplies, when an output signal of a connection destination neuron circuit changes and when the router receives the first address information identifying this connection destination neuron circuit via a bus, an update signal based on the changed output signal to one of the neuron circuits in accordance with the received first address information, the previously specified second address information identifying the first ising device, and the connection destination information.

First claim

What is claimed is:

1. An information processing apparatus comprising:
a plurality of ising devices connected to common buses; and
a processor,
each of the plurality of ising devices includes:
a plurality of neuron circuits, each of which calculates a first value based on a sum of values, each of which is obtained by multiplying an output signal of one of a plurality of connection destination neuron circuits by one of a plurality of weight values that indicate connection strength with the respective connection destination neuron circuits, outputs 0 or 1 in accordance with a result of comparison between a second value obtained by adding a noise value to the first value and a threshold, and updates, upon receiving an update signal when one of the output signals changes, the first value in accordance with the update signal,
a memory that holds items of connection destination information for each of the plurality of neuron circuits, each of the items of connection destination information including items of first address information identifying each of the plurality of connection destination neuron circuits and an item of second address information identifying, among the plurality of ising devices, a first ising device including at least one of the plurality of connection destination neuron circuits, the first and second address information being associated with each other, and
a router that supplies, when a first output signal of a first connection destination neuron circuit among the plurality of connection destination neuron circuits that is included in the first ising device changes and when the router receives the first address information identifying the first connection destination neuron circuit via one of the buses, the update signal based on a value of the changed first output signal transmitted via one of the buses to one of the plurality of neuron circuits in accordance with the received first address information, previously specified second address information identifying the first ising device, and the connection destination information, and
the processor specifies the second address information identifying the first ising device including the first connection destination neuron circuit that allows change of the first output signal, and
a certain neuron circuit among the plurality of neuron circuits included in the first ising device connects with all of the plurality of neuron circuits included in the first ising device other than the certain neuron circuit and connects with a part of the plurality of neuron circuits included in a second ising device of the plurality of ising devices, and the certain neuron circuit does not connect with other part of the plurality of neuron circuits included in the second ising device, and
a first number is greater than a second number, the first number indicates a number of the neuron circuits included in the first ising device and connected with the certain neuron circuit, and the second number indicates a number of the neuron circuits included in the second ising device and connected with the certain neuron circuit,
the router in a certain ising device of the plurality of ising devices compares the received first address information and the previously specified second address information identifying the first ising device with each of the items of connection destination information,
the router in the certain ising device supplies the update signal to one of the plurality of neuron circuits in the certain ising device when the received first address information and the previously specified second address information are included in one of the items of connection destination information, and
the router in the certain ising device keeps the output signal of the one of the plurality of neuron circuits when the received first address information and the previously specified second address information are not included in the one of the items of connection destination information.

2. The information processing apparatus according to claim 1 , wherein, when the first output signal of the first connection destination neuron circuit changes, the router included in the first ising device supplies the changed value of the first output signal and the first address information identifying the first connection destination neuron circuit to the buses.

3. The information processing apparatus according to claim 1 , wherein each of the plurality of ising devices includes a storage unit holding a same second address information specified by the processor.

4. The information processing apparatus according to claim 1 , wherein
the second ising device includes a memory in which the connection destination information is stored, and
in the connection destination information, the first address information identifying the first connection destination neuron circuit included in the first ising device is associated with identification information, which identifies the first connection destination neuron circuit, used inside the second ising device.

5. The information processing apparatus according to claim 1 , wherein
a plurality of connection destination neuron circuits of a plurality of neuron circuits arranged in a third ising device among the plurality of ising devices include a plurality of second connection destination neuron circuits of the plurality of neuron circuits included in the third ising device and a plurality of third connection destination neuron circuits included in one or a plurality of fourth ising devices among the plurality of ising devices, and
a number of the third connection destination neuron circuits is less than a number of the second connection destination neuron circuits.

6. An ising device comprising:
a plurality of neuron circuits, each of which calculates a first value based on a sum of values, each of which is obtained by multiplying an output signal of one of a plurality of connection destination neuron circuits by one of a plurality of weight values that indicate connection strength with the respective connection destination neuron circuits, outputs 0 or 1 in accordance with a result of comparison between a second value obtained by adding a noise value to the first value and a threshold, and updates, upon receiving an update signal when one of the output signals changes, the first value in accordance with the update signal;
a memory that holds items of connection destination information for each of the plurality of neuron circuits, each of the items of connection destination information including items of first address information identifying each of the plurality of connection destination neuron circuits and an item of second address information identifying, among a plurality of ising devices connected to common buses, a first ising device including at least one of the plurality of connection destination neuron circuits, the first and second address information being associated with each other; and
a router that supplies, when a first output signal of a first connection destination neuron circuit among the plurality of connection destination neuron circuits that is included in the first ising device changes and when the router receives the first address information identifying the first connection destination neuron circuit via one of the buses, the update signal based on a value of the changed first output signal transmitted via one of the buses to one of the plurality of neuron circuits in accordance with the received first address information, previously specified second address information identifying the first ising device, and the connection destination information,
a certain neuron circuit among the plurality of neuron circuits included in the ising device connects with all of the plurality of neuron circuits included in the isin

Assignees

• Fujitsu Ltd

Inventors

• Tsukamoto Sanroku
• Tamura Hirotaka
• Matsubara Satoshi

Classifications

• G06N3/047

  Probabilistic or stochastic networks · CPC title

• G06N3/044

  Recurrent networks, e.g. Hopfield networks · CPC title

• G06N3/04

  Architecture, e.g. interconnection topology · CPC title

• G06N3/063 Primary

  using electronic means · CPC title

• G06N3/0495

  Quantised networks; Sparse networks; Compressed networks · CPC title