Fast dynamic capacitance, frequency, and/or voltage throttling apparatus and method

Patent metadata

Field	Value
Publication number	US-11275663-B2
Application number	US-202016896070-A
Country	US
Kind code	B2
Filing date	Jun 8, 2020
Priority date	Jun 8, 2020
Publication date	Mar 15, 2022
Grant date	Mar 15, 2022

Abstract

A dedicated pin of a processor or system-on-chip (SoC) is used to indicate whether power level (e.g., charge, voltage, and/or current) of a battery falls below a threshold. The threshold can be predetermined or programmable. The battery is used to provide power to the processor and/or SoC. Upon determining that the power level of the battery falls below the threshold, the processor by-passes the conventional process of entering low performance or power mode, and directly throttles voltage and/or operating frequency of the processor. This allows the processor to continue to operate at low battery power. The fast transition (e.g., approximately 10 μS) from an active state to a low performance or power mode, in accordance with a logic level of the voltage on the dedicated pin, reduces decoupling capacitor design requirements, and makes it possible for the processor to adapt higher package power control settings (e.g., PL4).

First claim

What is claimed is:

1. A processor comprising:
a pin to receive an indication about battery charge relative to a threshold;
one or more processor cores; and
a power control unit to process the indication from the pin and determine whether to fast throttle the one or more processor cores, wherein to fast throttle the one or more processor cores, the power control unit is to bypass a legacy dynamic voltage and frequency scaling flow and directly throttle the one or more processor cores, and wherein the power control unit is to postpone the fast throttle if the processor is in a first power state.

2. The processor of claim 1 , further comprising a register to set a bit to enable or disable the fast throttle.

3. The processor of claim 2 , wherein the register includes one or more fields for throttle levels.

4. The processor of claim 3 , further comprising a lookup table to store the throttle levels.

5. The processor of claim 2 , wherein the bit for the register is set at reset.

6. The processor of claim 1 , wherein the threshold is programmable.

7. The processor of claim 1 , wherein to fast throttle the one or more cores comprises lower frequency, voltage, and/or capacitance of the one or more cores.

8. The processor of claim 1 , wherein the first power state is C6 power state.

9. An apparatus comprising:
a pin to receive an indication about battery charge relative to a threshold;
one or more processor cores; and
a power control unit to process the indication from the pin and determine whether to fast throttle the one or more processor cores, wherein the power control unit is to postpone the fast throttle if any of the one or more processor cores is in a C6 power state.

10. The apparatus of claim 9 , wherein to fast throttle the one or more processor cores, the power control unit is to bypass legacy dynamic voltage and frequency scaling flow and directly throttle the one or more cores.

11. The apparatus of claim 9 , further comprising a register to set a bit to enable or disable the fast throttle.

12. The apparatus of claim 11 , wherein the register includes one or more fields for throttle levels.

13. The apparatus of claim 12 , further comprising a lookup table to store the throttle levels.

14. The apparatus of claim 12 , wherein the bit for the register is set at reset.

15. The apparatus of claim 9 , wherein the threshold is programmable.

16. The apparatus of claim 9 , wherein to fast throttle the one or more cores comprises lower frequency, voltage, and/or capacitance of the one or more cores.

17. A system comprising:
a memory;
a processor coupled to the memory;
a battery to power the processor; and
a fuel gauge to monitor charge level of the battery with reference to a threshold, wherein an output of the fuel gauge is provided to a pin of the processor, wherein the processor comprises:
one or more processor cores; and
a power control unit to process an indication from the pin and determine whether to fast throttle the one or more cores based on a logic level of the pin, wherein to fast throttle the one or more processor cores, the power control unit is to bypass legacy dynamic voltage and frequency scaling flow and directly throttle the one or more processor cores, and wherein the power control unit is to postpone the fast throttle if the processor is in a first power state.

18. The system of claim 17 , wherein the processor comprises a register to set a bit to enable or disable the fast throttle, wherein the register includes field for throttle levels.

19. The system of claim 17 , wherein the processor comprises a lookup table to store the throttle levels.

20. The system of claim 17 , wherein the first power state is C6 power state.

Assignees

• Intel Corp

Inventors

• Gendler Alexander
• Angel Nimrod
• Ambardekar Ameya
• Wijeratne Sapumal
• Vij Vikas
• Schiff Tod
• Uan-Zo-Li Alexander

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/3296 Primary

  by lowering the supply or operating voltage · CPC title

• G06F15/7807

  System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package · CPC title

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F11/076

  by exceeding a count or rate limit, e.g. word- or bit count limit · CPC title