Readout circuit for a silicon photomultiplier (SiPM) array using charge sharing and anger logic
US-10451748-B1 · Oct 22, 2019 · US
US11275186B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11275186-B2 |
| Application number | US-201916668245-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 30, 2019 |
| Priority date | Aug 26, 2019 |
| Publication date | Mar 15, 2022 |
| Grant date | Mar 15, 2022 |
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An imaging device may include single-photon avalanche diodes (SPADs). Positioning SPADs close together in an imaging device (such as a silicon photomultiplier) may have benefits such as improved sensitivity. However, as the SPADs get closer together, the SPADS may become susceptible to crosstalk. Crosstalk is typically undesirable due to reduced dynamic range and reduced signal accuracy. To reduce crosstalk, a capacitor or other component may be coupled between adjacent SPADs. When an avalanche occurs on a given SPAD, the bias voltage may drop below the breakdown voltage. The capacitor may cause a corresponding voltage drop on a neighboring SPAD. The voltage drop on the neighboring SPAD reduces the over-bias of that SPAD, reducing the sensitivity of the SPAD and therefore mitigating the chance of crosstalk occurring.
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What is claimed is: 1. A silicon photomultiplier, comprising: a first microcell that includes a first single-photon avalanche diode and first quenching circuitry; a second microcell that includes a second single-photon avalanche diode and second quenching circuitry; and a capacitor coupled between the first microcell and the second microcell that causes a drop in voltage at the second single-photon avalanche diode in response to an avalanche occurring in the first single-photon avalanche diode to mitigate crosstalk between the first and second microcells, wherein the capacitor has a first plate that is coupled to a selected one of a cathode and an anode of the first single-photon avalanche diode, wherein the capacitor has a second plate that is coupled to a selected one of a cathode and an anode of the second single-photon avalanche diode, wherein the first plate comprises a layer of metal that is formed between the first and second microcells, and wherein the second plate comprises a layer of polysilicon that is formed between the first and second microcells. 2. The silicon photomultiplier defined in claim 1 , wherein the first plate is coupled to the cathode of the first single-photon avalanche diode and wherein the second plate is coupled to the cathode of the second single-photon avalanche diode. 3. The silicon photomultiplier defined in claim 1 , wherein the first plate is coupled to a first node that is interposed between the first single-photon avalanche diode and the first quenching circuitry and wherein the second plate is coupled to a second node that is interposed between the second single-photon avalanche diode and the second quenching circuitry. 4. The silicon photomultiplier defined in claim 1 , wherein the capacitor is a first capacitor, the silicon photomultiplier further comprising: a third microcell that includes a third single-photon avalanche diode and third quenching circuitry; and a second capacitor that is coupled between the first single-photon avalanche diode and the third single-photon avalanche diode. 5. The silicon photomultiplier defined in claim 4 , further comprising: a fourth microcell that includes a fourth single-photon avalanche diode and fourth quenching circuitry; a fifth microcell that includes a fifth single-photon avalanche diode and fifth quenching circuitry; a third capacitor that is coupled between the first single-photon avalanche diode and the fourth single-photon avalanche diode; and a fourth capacitor that is coupled between the first single-photon avalanche diode and the fifth single-photon avalanche diode. 6. The silicon photomultiplier defined in claim 1 , wherein the capacitor has a capacitance that is between 2 and 12 femtofarads.
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