Data converter false saturation detector

US11275127B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11275127-B2
Application numberUS-201916715492-A
CountryUS
Kind codeB2
Filing dateDec 16, 2019
Priority dateDec 16, 2019
Publication dateMar 15, 2022
Grant dateMar 15, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

Official abstract text for this publication.

According to aspects of the disclosure, an apparatus is disclosed comprising: a controller; an analog-to-digital converter (ADC) coupled to the controller, the ADC including an input terminal for receiving a sensor signal from a transducer; and a diagnostic circuit coupled to the input terminal of the ADC and to the controller, the diagnostic circuit being configured to: generate a diagnostic signal that indicates whether a voltage at the input terminal of the ADC meets a first threshold, and provide the diagnostic signal to the controller, wherein the controller is configured to: receive a data sample from the ADC, detect whether the data sample meets a second threshold, and transition the apparatus into a safe state when: (i) the diagnostic signal indicates that the voltage at the input terminal does not meet the first threshold, and (ii) the data sample meets the second threshold.

First claim

Opening claim text (preview).

What is claimed is: 1. A sensor comprising: a controller; a transducer arranged to produce a first sensor signal and a second sensor signal; an analog-to-digital converter (ADC) having a first input terminal and a second input terminal, the first input terminal being arranged to receive the first sensor signal, and the second input terminal being arranged to receive the second sensor signal; and a diagnostic circuit configured to: generate a first diagnostic signal that indicates whether a first voltage at the first input terminal meets a first threshold, and provide the first diagnostic signal to the controller; and generate a second diagnostic signal that indicates whether a second voltage at the second input terminal meets the first threshold, and provide the second diagnostic signal to the controller, wherein the controller is configured to: receive a data sample that is generated by the ADC, detect whether the data sample meets a second threshold or a third threshold, the second threshold being based on a full-scale low value of the ADC and the third threshold being based on a full-scale high value of the ADC; when the data sample meets the second threshold: detect whether the first voltage exceeds the first threshold based on the first diagnostic signal, transition the sensor into a first safe state when the first voltage does not meet the first threshold, and generate an output signal based on the data sample when the first voltage meets the first threshold; when the data sample meets the third threshold: detect whether the second voltage meets the first threshold based on the second diagnostic signal, transition the sensor into a second safe state when the second voltage does not meet the first threshold, and generate an output signal based on the data sample when the second voltage meets the first threshold. 2. The sensor of claim 1 , wherein the diagnostic circuit includes: a first voltage comparator that is arranged to compare the first sensor signal to the first threshold, and output the first diagnostic signal based on an outcome of the comparison of the first sensor signal to the first threshold; and a second voltage comparator that is arranged to compare the second sensor signal to the first threshold, and output the second diagnostic signal based on an outcome of the comparison of the second sensor signal to the first threshold. 3. The sensor of claim 1 , wherein generating the first diagnostic signal includes imparting a first value on the first diagnostic signal when the first voltage meets the first threshold, and imparting a second value on the first diagnostic signal when the first voltage does not meet the first threshold. 4. The sensor of claim 1 , wherein transitioning the sensor into the first safe state includes discarding the data sample. 5. The sensor of claim 1 , wherein transitioning the sensor into the first safe state includes at least one of resetting the ADC and outputting an error code. 6. The sensor of claim 1 , wherein the ADC includes a sigma-delta converter. 7. The sensor of claim 1 , wherein the transducer includes at least one of a giant magnetoresistance (GMR) sensing element, a Hall effect element, and a tunnel magnetoresistance (TMR) element. 8. The sensor of claim 1 , wherein the controller is further configured to execute a test sequence in response to a predetermined input, the test sequence including causing the first voltage to exceed the first threshold and forcing the diagnostic circuit to set the first diagnostic signal to a first predetermined value. 9. The sensor of claim 8 , wherein performing the test sequence further includes causing the second voltage to exceed the first threshold and forcing the diagnostic circuit to set the second diagnostic signal to a second predetermined value. 10. An apparatus comprising: a controller; an analog-to-digital converter (ADC) coupled to the controller, the ADC including an input terminal for receiving a sensor signal from a transducer; and a diagnostic circuit coupled to the input terminal of the ADC and to the controller, the diagnostic circuit being configured to: generate a diagnostic signal that indicates whether a voltage at the input terminal of the ADC meets a first threshold, and provide the diagnostic signal to the controller, wherein the controller is configured to: receive a data sample that is generated by the ADC, detect whether the data sample meets a second threshold, and transition the apparatus into a safe state when: (i) the diagnostic signal indicates that the voltage at the input terminal does not meet the first threshold, and (ii) the data sample meets the second threshold, wherein the second threshold is based on one of a full-scale low value of the ADC or a full-scale high value of the ADC. 11. The apparatus of claim 10 , wherein the diagnostic circuit includes a voltage comparator that is arranged to compare the voltage to the first threshold, and output the diagnostic signal based on an outcome of the comparison. 12. The apparatus of claim 10 , wherein generating the diagnostic signal includes imparting a first value on the diagnostic signal when the voltage at the input terminal of the ADC meets the first threshold, and imparting a second value on the diagnostic signal when the voltage at the input terminal of the ADC does not meet the first threshold. 13. The apparatus of claim 10 , wherein the controller is further configured to generate an output signal based on the data sample when: (i) the diagnostic signal indicates that the voltage at the input terminal meets the first threshold, and (ii) the data sample meets the second threshold. 14. The apparatus of claim 10 , wherein transitioning the apparatus into the safe state includes discarding one or more data samples that are received from the ADC. 15. The apparatus of claim 10 , wherein transitioning the apparatus into the safe state includes at least one of resetting the ADC and outputting an error code. 16. The apparatus of claim 10 , wherein the ADC includes a sigma-delta converter. 17. The apparatus of claim 10 , wherein the transducer includes at least one of a giant magnetoresistance (GMR) sensing element, a Hall effect element, and a tunnel magnetoresistance (TMR) element. 18. The apparatus of claim 10 , wherein the controller is further configured to execute a test sequence in response to a predetermined input, the test sequence including causing the voltage at the input terminal to exceed the first threshold and forcing the diagnostic circuit to set the diagnostic signal to a predetermined value. 19. A method for use in a sensor, comprising: generating, by a diagnostic circuit, a diagnostic signal that indicates whether a voltage at an input terminal of an analog-to-digital converter (ADC) meets a first threshold; providing, by the diagnostic circuit, the diagnostic signal to a controller; receiving, by the controller, a data sample that is generated by the ADC; detecting, by the controller, whether the data sample meets a second threshold; and transitioning into a safe state when: (i) the diagnostic signal indicates that the voltage at the input terminal does not meet the first threshold, and (ii) the data sample meets the second threshold, wherein the second threshold is based on one of a full-scale low value of the ADC or a full-scale high value of the ADC. 20. The method of claim 19 , further comprising executing a test sequence in response to a predetermined input, the test sequence including causing the vol

Assignees

Inventors

Classifications

  • Measuring direction or magnitude of magnetic fields or magnetic flux (G01R33/20 takes precedence) · CPC title

  • Constructional adaptation of the sensor to specific applications · CPC title

  • Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

  • Detection or location of converter hardware failure, e.g. power supply failure, open or short circuit · CPC title

  • Testing or calibrating of apparatus covered by the other groups of this subclass · CPC title

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Frequently asked questions

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What does patent US11275127B2 cover?
According to aspects of the disclosure, an apparatus is disclosed comprising: a controller; an analog-to-digital converter (ADC) coupled to the controller, the ADC including an input terminal for receiving a sensor signal from a transducer; and a diagnostic circuit coupled to the input terminal of the ADC and to the controller, the diagnostic circuit being configured to: generate a diagnostic s…
Who is the assignee on this patent?
Allegro Microsystems Llc
What technology area does this patent fall under?
Primary CPC classification G01R33/0023. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Mar 15 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).