Programmable scan compression

Patent metadata

Field	Value
Publication number	US-11275112-B2
Application number	US-202017002687-A
Country	US
Kind code	B2
Filing date	Aug 25, 2020
Priority date	May 30, 2018
Publication date	Mar 15, 2022
Grant date	Mar 15, 2022

Abstract

An implementation of a system disclosed herein includes a decompressor logic with the capability to vary a level of decompression of a scanning input signal based on value of compression program bits and a compressor logic to generate a scanning output signal, the compressor logic including a plurality of XOR logics, wherein the output of the plurality of XOR logics is selected based on the compression program bits.

First claim

What is claimed is:

1. An apparatus, comprising:
a decompressor logic with the capability to decompress a scanning input signal to generate a decompressed signal; and
a plurality of multiplexers to multiplex the decompressed signal based on values of compression program bits onto a plurality of scan chains such that length of the plurality of scan chains traversed by the decompressed signal is determined by the values of the compression program bits, wherein each of the plurality of scan chains is communicatively connected to one of a plurality of comparators configured in a compressor logic.

2. The apparatus of claim 1 , wherein the compressor logic configured to receive output from the plurality of scan chains and to generate a scanning output signal, the compressor logic including a plurality of XOR logics, wherein the output of the plurality of XOR logics is selected based on the values of the compression program bits.

3. The apparatus of claim 2 , wherein the plurality of multiplexers controlling the input to the plurality of scan chains, wherein one of the compression program bits is input as a control bit for the one or more of the plurality of multiplexers.

4. The apparatus of claim 3 , wherein the compressor logic further comprising one or more AND gates and an input to the one or more AND gates is an output signal from the XOR logics.

5. The apparatus of claim 4 , wherein another input to the one or more AND gates is the one of the compression program bits.

6. The apparatus of claim 1 , wherein compression program bits include two-bits that allows the level of compression of the scanning input signal at three different levels.

7. The apparatus of claim 1 , wherein scan compression program bits include one-bit that allows the level of compression of the scanning signal at two different levels of Cx and 0.5Cx, wherein Cx being maximum compression.

8. A programmable scan controller, comprising:
a decompressor logic, configured to decompress a scanning input signal to generate a decompressed signal; and
a plurality of multiplexers to multiplex the decompressed signal based on values of compression program bits onto a plurality of scan chains such that length of the plurality of scan chains traversed by the decompressed signal is determined by the values of the compression program bits, wherein each of the plurality of scan chains is communicatively connected to one of a plurality of comparators configured in a compressor logic.

9. The programmable scan controller of claim 8 , wherein the compressor logic configured to receive output from the plurality of scan chains and to generate a scanning output signal, the compressor logic including a plurality of XOR logics, wherein the output of the plurality of XOR logics is selected based on the values of the compression program bits.

10. The programmable scan controller of claim 9 , wherein the decompressed signal is input to the plurality of scan chains and the signal output from the plurality scan chains is input to the compressor logic.

11. The programmable scan controller of claim 9 , wherein the compressor logioc further comprising one or more AND gates and an input to the one or more end gates is an output signal from the XOR logics.

12. The programmable scan controller of claim 9 , wherein another input to the one or more AND gates is the one of the compression program bits.

13. The programmable scan controller of claim 9 , wherein the compression program bits include two-bits with values that allows the level of compression of the scanning input signal at three different levels.

14. The programmable scan controller of claim 9 , wherein the compression program bits include one-bit with value that allows the level of compression of the scanning signal at two different levels of Cx and 0.5Cx, wherein Cx being maximum compression.

15. A test structure of an integrated circuit (IC), comprising:
a decompressor logic with the capability to vary a level of decompression of decompress a scanning input signal to generate a decompressed signal;
a plurality of multiplexers to multiplex the decompressed signal based on values of compression program bits onto a plurality of scan chains such that length of the plurality of scan chains traversed by the decompressed signal is determined by the values of the compression program bits, wherein each of the plurality of scan chains is communicatively connected to one of a plurality of comparators configured in a compressor logic.

16. The test structure of claim 15 , wherein the compressor logic to configured to receive output from the plurality of scan chains and generate a scanning output signal, the compressor logic including a plurality of XOR logics, wherein the output of the plurality of XOR logics is selected based on the values of the compression program bits.

17. The test structure of claim 16 wherein a decompressed scanning signal is input to a plurality of scan chains and the signal output from the plurality scan chains is input to the compressor logic.

18. The test structure of claim 17 , wherein the length of the scan chain traversed by the scanning input signal is determined by the value of the compression program bits.

19. The test structure of claim 16 , wherein compression program bits include two-bits that allows the level of compression of the decompressed signal at three different levels.

20. The test structure of claim 16 , wherein scan compression program bits include one-bit that allows the level of compression of the scanning signal at two different levels of Cx and 0.5Cx, wherein Cx being maximum compression.

Assignees

• Seagate Technology Llc

Inventors

• Londhe Bharat P
• Shah Jay
• Bhasale Aniruddha M

Classifications

• G01R31/31813

  Test pattern generators · CPC title

• G01R31/318547 Primary

  Data generators or compressors · CPC title

• G01R31/31724

  Test controller, e.g. BIST state machine (for scan test G01R31/318555) · CPC title

• G01R31/3177

  Testing of logic operation, e.g. by logic analysers · CPC title

• G01R31/318533

  using scanning techniques, e.g. LSSD, Boundary Scan, JTAG · CPC title