Amplification interface, and corresponding measurement system and method for calibrating an amplification interface

Patent metadata

Field	Value
Publication number	US-11275100-B2
Application number	US-202016781598-A
Country	US
Kind code	B2
Filing date	Feb 4, 2020
Priority date	Feb 8, 2019
Publication date	Mar 15, 2022
Grant date	Mar 15, 2022

Abstract

An amplification interface includes an input terminal receiving a sensor current and an output terminal supplying an output voltage. An analog integrator is connected to the input terminal and supplies the output voltage. A current generator is connected to the input of the analog integrator and generates a compensation current based on a drive signal. A control circuit generates the drive signal for the current generator based on a control signal representing an offset in the sensor current supplied by the sensor. The current generator generates, based on the driving signal, a positive or negative current. The control circuit determines a first duration and a second duration as a function of the control signal representing the offset in the sensor current, during the measurement interval, and sets the driving signal to a first logic value for the first duration and to a second logic value for the second duration.

First claim

The invention claimed is:

1. An amplification interface, comprising:
an input terminal configured to receive a sensor current;
an output terminal configured to provide an output voltage;
an analog integrator, wherein an input of said analog integrator is connected to the input terminal, wherein an output of said analog integrator provides said output voltage, wherein said analog integrator is configured to be reset or activated via a reset signal, wherein:
when said analog integrator is reset, said output voltage corresponds to a reference voltage; and
when said analog integrator is activated, said output voltage varies as a function of a current received at the input of said analog integrator;

a current generator, wherein an output of said current generator is connected to the input of said analog integrator, wherein said current generator is configured to generate at the output of said current generator a compensation current as a function of a drive signal;
a control circuit configured to:
generate said reset signal, such that said analog integrator is periodically reset during a reset interval and activated during a measurement interval;
receive a control signal indicative of an offset in said sensor current; and
generate said drive signal as a function of said control signal indicative of the offset in said sensor current;

wherein said current generator is configured to:
when said drive signal has a first logic value, generate at the output of said current generator a positive current; and
when said drive signal has a second logic value, generate at the output of said current generator a negative current; and

wherein said control circuit is further configured to:
determine a first duration and a second duration as a function of said control signal indicative of the offset in said sensor current, wherein a sum of said first duration and said second duration corresponds to a duration of said measurement interval; and
during said measurement interval, set said drive signal to said first logic value for said first duration and set said drive signal to said second logic value for said second duration.

2. The amplification interface according to claim 1 , wherein said positive current and said negative current have a same amplitude but opposite signs.

3. The amplification interface according to claim 1 , wherein said current generator comprises:
a first current generator configured to generate said positive current; and
a second current generator configured to generate said negative current.

4. The amplification interface according to claim 3 , wherein said current generator comprises:
circuitry to selectively enable said first current generator or said second current generator as a function of said drive signal; or
circuitry to selectively connect said first current generator or said second current generator to the output of said current generator as a function of said drive signal.

5. The amplification interface according to claim 1 , wherein said control circuit is configured to generate said reset signal and said drive signal via a counter circuit in a synchronous manner in response to a clock signal.

6. The amplification interface according to claim 5 , wherein said measurement interval corresponds to an even number of 2N sub-intervals, wherein a duration of each sub-interval corresponds to a multiple of a period of said clock signal, wherein N is an integer.

7. The amplification interface according to claim 6 , wherein said control circuit is configured to determine said first duration, T 4 , and said second duration, T 5 , as:

T
4

=

T
2

2

-

C
⁢
O
⁢
M
⁢
P
⁢

T
2

2
⁢
N

T
5

=

T
2

2

+

COMP
⁢

T
2

2
⁢
N

where T 2 is the duration of said measurement interval, and COMP is an integer number between −N and +N and corresponds to said control signal indicative of an offset in said sensor current.

8. The amplification interface according to claim 1 , wherein said analog integrator comprises an operational amplifier, wherein a first input terminal of said operational amplifier is connected via a capacitor to an output terminal of said operational amplifier and a second input terminal of said operational amplifier is connected to a reference voltage.

9. The amplification interface according to claim 8 , wherein said analog integrator comprises an electronic switch connected in parallel with said capacitor, and wherein said electronic switch is configured to:
when said reset signal has a first logic value, close said electronic switch; and
when said reset signal has a second logic value, open said electronic switch.

10. The amplification interface according to claim 1 , further comprising a sample-and-hold circuit configured to:
when a sampling signal has a first logic value, store said output voltage at the output of said analog integrator; and
when said sampling signal has a second logic value, maintain stored said output voltage at the output of said analog integrator;
wherein said control circuit is further configured to, during said measurement interval, set said sampling signal to said first logic value for a sampling duration and set said sampling signal to said second logic value for a hold duration.

11. A method of calibrating the amplification interface of claim 1 , the method comprising:
connecting said sensor current to the input terminal of said amplification interface;
monitoring, at an end of said measurement interval, the output voltage at the output terminal of said amplification interface; and
varying said control signal such that said monitored output voltage corresponds to said reference voltage.

12. A measurement system, comprising:
an amplificat

Assignees

• St Microelectronics Srl

Inventors

• Vaiana Michele
• Ippolito Calogero Marco
• Recchia Angelo
• Cicero Antonio
• Lombardo Pierpaolo

Classifications

• H03F2203/45514

  the FBC comprising one or more switched capacitors, and being coupled between the LC and the IC · CPC title

• G01R19/0069

  measuring voltage or current standards · CPC title

• H03F1/0205

  in transistor amplifiers · CPC title

• H03F3/4565

  Controlling the common source circuit of the differential amplifier · CPC title

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title