System and method for supporting scalable bit map based P_Key table in a high performance computing environment

Patent metadata

Field	Value
Publication number	US-11271870-B2
Application number	US-201715412972-A
Country	US
Kind code	B2
Filing date	Jan 23, 2017
Priority date	Jan 27, 2016
Publication date	Mar 8, 2022
Grant date	Mar 8, 2022

Abstract

System and method for supporting scalable bitmap based P_Key table in a high performance computing environment. A method can provide, at least one subnet comprising one or more switches, a plurality of host channel adapters, and a plurality of end nodes. The method can associate the plurality of end nodes with at least one of a plurality of partitions, wherein each of the plurality of partitions are associated with a P_Key value. The method can associate each of the one or more switches with a bitmap based P_Key table of a plurality of bitmap based P_Key tables. The method can associate each of the host channel adapters with a bitmap based P_Key table of the plurality of bitmap based P_Key tables.

First claim

What is claimed is:

1. A system for supporting a bitmap based P_Key table in a high performance computing environment, comprising:
one or more microprocessors;
at least one subnet, the at least one subnet comprising
a plurality of switches, the plurality of switches being arranged in a plurality of levels comprising at least a leaf switch level, an intermediate switch level, and a root switch level, wherein each of the plurality of switches comprises a plurality of switch ports,
a plurality of host channel adapters, each host channel adapter comprising at least one host channel adapter port of a plurality of host channel adapter ports, and
a plurality of end nodes, wherein each of the plurality of end nodes is associated with at least one host channel adapter of the plurality of host channel adapters;

wherein each of the plurality of end nodes is associated with at least one of a plurality of partitions;
wherein each of the plurality of partitions is associated with a P_Key value of a plurality of P_Key values;
wherein each switch port of the plurality of switch ports is associated with at least one bitmap of a plurality of bitmaps, each respective bitmap being stored in a memory of each respective switch, wherein each bitmap comprises an array comprising a mapping of a representation of each of the plurality of P_Key values to a corresponding bit of a plurality of bits of the array, each bit corresponding to a value of allowed or disallowed;
wherein upon a switch port of a switch at non-leaf level receiving a packet from a sending end node, the packet comprising a header comprising a destination local identifier (DLID) of a receiving end node and a P_Key value indicating the sending end node belongs to a partition being associated with the P_Key, the sending end node being a full member of the partition and the receiving end node being a limited member of the partition, the at least one bitmap is indexed by the P_Key value of the header of the received packet to determine an allowed value for the received packet; and
wherein upon the switch port receiving another packet from another sending end node, the another packet comprising a header comprising the DLID of the receiving end node and the P_Key value indicating the another sending end node belongs to the same partition being associated with the P_Key, the another sending end node being a limited member of the partition, the at least one bitmap is indexed by the P_Key value of the header of the received another packet to determine a disallowed value for the another received packet.

2. The system of claim 1 , further comprising:
a subnet manager, the subnet manager running on one of the plurality of switches or one of the plurality of host channel adapters;
wherein the subnet manager determines allowed and disallowed traffic through the plurality of ports on each of the one or more switches.

3. The system of claim 2 ,
wherein the subnet manager configures each of the plurality of bitmaps based upon the determination of allowed and disallowed traffic through each of the plurality of ports on each of the one or more switches.

4. The system of claim 1
wherein a host channel adapter port of the plurality of host channel adapter ports is associated with at least another bitmap of the plurality of bitmaps, wherein the at least another bitmap comprises an array comprising a mapping of a representation of each of the plurality of P_Key values to a value of allowed or disallowed.

5. The system of claim 4 , wherein upon receiving an allowed value, the switch allows the packet to pass through the addressed port.

6. The system of claim 4 , wherein upon receiving a disallowed value, the switch drops the packet at the addressed port.

7. The system of claim 1 , wherein the one or more subnets comprise two or more subnets, each of the two or more subnets being interconnected by at least one router in each of the two or more subnets.

8. A method for supporting a bitmap based P_Key table in a high performance computing environment, comprising:
providing, at one or more computers, including one or more microprocessors,
at least one subnet, the at least one subnet comprising
a plurality of switches, the plurality of switches being arranged in a plurality of levels comprising at least a leaf switch level, an intermediate switch level, and a root switch level, wherein each of the plurality of switches comprises a plurality of switch port,
a plurality of host channel adapters, each host channel adapter comprising at least one host channel adapter port of a plurality of host channel adapter ports, and
a plurality of end nodes, wherein each of the plurality of end nodes is associated with at least one host channel adapter of the plurality of host channel adapters;

associating each of the plurality of end nodes with at least one of a plurality of partitions, wherein each of the plurality of partitions is associated with a P_Key value of a plurality of P_Key values;
associating each switch port of the plurality of switch ports with at least one bitmap of a plurality of bitmaps, each respective bitmap being stored in a memory of each respective switch, wherein each bitmap comprises an array comprising a mapping of a representation of each of the plurality of P_Key values to a corresponding bit of a plurality of bits of the array, each bit corresponding to a value of allowed or disallowed;
upon a switch port of a switch at non-leaf level receiving a packet from a sending end node, the packet comprising a header comprising a destination local identifier (DLID) of a receiving end node and a P_Key value indicating the sending end node belongs to a partition being associated with the P_Key, the sending end node being a full member of the partition and the receiving end node being a limited member of the partition, indexing the at least one bitmap bar the P_Key value of the header of the received packet to determine an allowed disallowed value for the received packet; and
upon the switch port receiving another packet from another sending end node, the another packet comprising a header comprising the DLID of the receiving end node and the P_Key value indicating the another sending end node belongs to the same partition being associated with the P_Key, the another sending end node being a limited member of the partition, indexing the at least one bitmap by the P_Key value of the header of the received another packet to determine a disallowed value for the another received packet.

9. The method of claim 8 , further comprising:
further providing, at the one or more computers, including the one or more microprocessors, a subnet manager, the subnet manager running on one of the plurality of switches or one of the plurality of host channel adapters; and
determining, by the subnet manager, allowed and disallowed traffic through the plurality of ports on each of the one or more switches.

10. The method of claim 9 further comprising,
configuring, by the subnet manager, each of the plurality of bitmap based upon the determination of allowed and disallowed traffic through each of the plurality of ports on each of the one or more switches.

11. The method of claim 8 , further comprising:
associating a host channel adapter port of the plurality of host channel adapter ports with at least another bitmap of the plurality of bitmaps, wherein the at least another bitmap comprises an array comprising a mapping of a representation of each of the plurality of P_Key values to a value of allowed or disallowed.

12. The method of claim 11 , further comprising:
upon receiving an allowed value, allowing, by the switch, the packet to pass through the a

Assignees

• Oracle Int Corp

Inventors

• Johnsen Bjørn Dag
• Srinivasan Arvind
• Holen Line

Classifications

• H04L45/48

  Routing tree calculation · CPC title

• H04L45/02

  Topology update or discovery · CPC title

• H04L49/112

  Switch control, e.g. arbitration · CPC title

• H04L49/111

  Switch interfaces, e.g. port details · CPC title

• H04L45/484

  using multiple routing trees · CPC title