Arrangement and method for connecting various integrated circuits in an automotive control system

Patent metadata

Field	Value
Publication number	US-11271773-B2
Application number	US-201816621671-A
Country	US
Kind code	B2
Filing date	Jun 14, 2018
Priority date	Jun 14, 2017
Publication date	Mar 8, 2022
Grant date	Mar 8, 2022

Abstract

The invention relates to an arrangement and a method performing data exchange between various integrated circuits, IC, (3,4,5,6,7) in an automotive control system wherein the data are exchanged by a bus and has the object to enable ASIL C/D system coverage and to tie various ICs (clocks, regulators, memory interfaces, sensor signal conditioners, power management ICs etc.) This is solved the data are exchanged by a bus being ASIL C/D compliant and forming a common protocol to exchange information among the integrated circuits (3,4,5,6,7). The method is solved by functions implemented within the bus as setting the frequency of operation; arbitrating roles of the integrated circuits as master or slave device; checking integrity of exchanged data; frame repetition; detecting bus stuck-at failure modes; filtering or denouncing failures and warnings from peripheral devices; detecting remote out of specification local clock; and monitoring and predicting system reliability and profiling maintenance events.

First claim

The invention claimed is:

1. An arrangement for connecting various integrated circuits in an automotive control system wherein at least two integrated circuits are connected by a bus being ASIL C/D compliant and forming a common bus protocol to exchange information among the integrated circuits, the arrangement comprising:
a means for setting the frequency of operation, the frequency of operation adopted to ensure safe function of the at least two integrated circuits;
a means for arbitrating roles of the at least two integrated circuits as master or slave device;
a means for checking integrity of exchanged data, wherein the means for checking integrity includes means for performing a cyclic redundancy check (CRC) of data transmitted between the at least two integrated circuits and means for performing a temporal redundant check of data transmitted between the at least two integrated circuits;
a means for frame repetition, which periodically gathers failures data information from each slave by a broadcast-inquiring by the master;
a mechanism to detect bus stuck-at failure modes by counting the rising or falling edge of single pulse width modulation (PWM) data signals;
a mechanism to filter or denounce failures and warnings from peripheral devices by validating and transferring to the bus failures having a duration longer than an expected time;
a means for detecting remote out of specification local clock by implementing a bit counter to install a remote clock timing check; and
a means for monitoring and predicting system reliability and profiling maintenance events by collecting precise temperature information about neighbor discrete components that are directly exposed to a junction temperature.

2. The arrangement of claim 1 , wherein the bus is configured as a single wire interface bus.

3. The arrangement of claim 1 , wherein the bus is configured to exchange telemetry information.

4. The arrangement of claim 3 , wherein the bus is designed to exchange information about temperature, voltage, current, fault conditions, warnings, frequency or mode of operation.

5. The arrangement of claim 1 , wherein the bus protocol is provided with an additional protocol layer implementing industry standard interfaces such as I2C, PMBUS, SMBUS, SVID, SPI, SCSI, PCIe or USB.

6. The arrangement of claim 1 , wherein a power management IC (PMIC) is connected with one or more digital processing units (DPU) via the bus.

7. The arrangement of claim 6 , wherein the power management IC (PMIC) is connected to an automotive SoC whereby the bus is safe controlling power delivery to the automotive SoC.

8. A method of performing data exchange between various integrated circuits in an automotive control system wherein the data are exchanged by a bus being ASIL C/D compliant and forming a common protocol to exchange information among the integrated circuits comprising the steps of
setting the frequency of operation to ensure safe function of the various integrated circuits;
arbitrating roles of the various integrated circuits as master or slave device;
checking integrity of exchanged data, wherein checking integrated includes performing a cyclic redundancy check (CRC) and a temporal redundant check of data transmitted between the various integrated circuits;
periodically gathering failures data information from each slave by a broadcast-inquiring by the master to provide frame repetition;
detecting bus stuck-at failure modes by counting the rising or falling edge of single pulse width modulation (PWM) data signals;
filtering or denouncing failures and warnings from peripheral devices by validating and transferring to the bus failures having a duration longer than an expected time;
detecting remote out of specification local clock by implementing a bit counter to install a remote clock timing check; and
monitoring and predicting system reliability and profiling maintenance events by collecting precise temperature information about neighbor discrete components that are directly exposed to a junction temperature.

9. The method of claim 8 , wherein telemetry information is exchanged.

10. The method of claim 9 , wherein information about temperature, voltage, current, fault conditions, warnings, frequency or mode of operation is exchanged.

11. The method of claim 8 , wherein the bus protocol is provided with an additional protocol layer implementing industry standard interfaces such as I2C, PMBUS, SMBUS, SVID, SPI, SCSI, PCIe or USB.

12. The method of claim 8 , wherein a power delivery to an automotive SoC is performed using safe controlling.

13. An arrangement for connecting various integrated circuits in an automotive control system wherein at least two integrated circuits are connected by a bus being ASIL C/D compliant and forming a common bus protocol to exchange information among the integrated circuits, the arrangement configured to
set the frequency of operation to ensure safe function of the various integrated circuits;
arbitrate roles of the various integrated circuits as master or slave device;
check integrity of exchanged data, which includes performing a cyclic redundancy check (CRC) and a temporal redundant check of data transmitted between the various integrated circuits;
periodically gather failures data information from each slave by a broadcast-inquiring by the master to provide frame repetition;
detect bus stuck-at failure modes by counting the rising or falling edge of single pulse width modulation (PWM) data signals;
filter or denounce failures and warnings from peripheral devices by validating and transferring to the bus failures having a duration longer than an expected time;
detect remote out of specification local clock by implementing a bit counter to install a remote clock timing check; and
monitor and predict system reliability and profiling maintenance events by collecting precise temperature information about neighbor discrete components that are directly exposed to a junction temperature.

14. The arrangement of claim 13 , wherein the bus is configured as a single wire interface bus.

15. The arrangement of claim 13 , wherein the bus is configured to exchange telemetry information.

16. The arrangement of claim 15 , wherein the bus is designed to exchange information about temperature, voltage, current, fault conditions, warnings, frequency or mode of operation.

17. The arrangement of claim 13 , wherein the bus protocol is provided with an additional protocol layer implementing industry standard interfaces such as I2C, PMBUS, SMBUS, SVID, SPI, SCSI, PCIe or USB.

18. The arrangement of claim 13 , wherein a power management IC (PMIC) is connected with one or more digital processing units (DPU) via the bus.

19. The arrangement of claim 18 , wherein the power management IC (PMIC) is connected to an automotive SoC whereby the bus is safe controlling power delivery to the automotive SoC.

Assignees

• Integrated Device Tech
• Renesas Electronics America Inc

Inventors

• Singh Manjit
• Di Matteo Serge
• Krellner Jan
• Kwok Kenneth C

Classifications

• H04L41/149

  for prediction of maintenance · CPC title

• H04L12/40176 Primary

  involving redundancy (error detection or correction of the data by redundancy in hardware using active fault-masking in interconnections G06F11/2002; error detection or correction of the data by redundancy in hardware using active fault-masking in storage systems using spares or by reconfiguring G06F11/2053) · CPC title

• H04L12/40169 Primary

  Flexible bus arrangements (arrangements for maintenance or administration involving management of faults; events, alarms H04L41/06; automatic restoration of network faults H04L41/0654) · CPC title

• G06F11/0745

  in an input/output transactions management context (input/output processing in general G06F13/00) · CPC title

• H04L12/40104

  Security; Encryption; Content protection (cryptographic protocols H04L9/00; protocols for network security H04L63/00) · CPC title