Medium voltage planar DC bus distributed capacitor array

Patent metadata

Field	Value
Publication number	US-11271492-B2
Application number	US-202016939914-A
Country	US
Kind code	B2
Filing date	Jul 27, 2020
Priority date	Jul 27, 2020
Publication date	Mar 8, 2022
Grant date	Mar 8, 2022

Abstract

An inverter with a modular bus assembly is described. In various embodiments, the modular bus assembly includes a laminated motherboard and a plurality of capacitor daughtercards. The laminated motherboard can be configured to interface a plurality of phase-leg modules and a plurality of capacitor daughtercards through a plurality of terminals and connectors located on a bottom side or a top side of the laminated motherboard. The laminated motherboard includes a layer stack with a plurality of conductor layers. Each of the plurality of conductor layers is implemented with a net spacing from a neighboring plated through hole (PTH) based at least in part on differences in potential to be applied to each of the plurality of conductor layers as compared to a potential to be applied to the PTH. Embedded shield polygons can be implemented on the laminated motherboard to mitigate surface discharge at surface terminal (PTH/SMT) triple junctions.

First claim

Therefore, at least the following is claimed:

1. An assembly configured for power delivery, comprising:
a plurality of distributed daughtercards forming a capacitor bank, each of the plurality of distributed daughtercards comprising an array of capacitors; and
a laminated motherboard for the assembly, the laminated motherboard configured to electrically interface the plurality of distributed daughtercards, each of the plurality of distributed daughtercards connecting to the laminated motherboard through a plurality of connectors located on a bottom side of the laminated motherboard, the plurality of distributed daughtercards and the laminated motherboard forming a modular direct current (DC) bus assembly, the laminated motherboard comprising:
a first phase-leg module, a second phase-leg module, and a third phase-leg module; and
a layer stack with a plurality of conductor layers for the first phase-leg module, the second phase-leg module, and the third phase-leg module.

2. The assembly of claim 1 , wherein the plurality of distributed daughtercards comprise low voltage distributed daughtercards, the plurality of distributed daughtercards being connected in a series configuration to form a medium voltage capacitor bank of a desired target voltage.

3. The assembly of claim 2 , wherein each node between any two consecutive distributed daughtercards in the series configuration of the plurality of distributed daughtercards connects to a dedicated conductor layer of the layer stack of the laminated motherboard.

4. The assembly of claim 1 , wherein each of the plurality of connectors connect to a dedicated conductor layer of the laminated motherboard.

5. The assembly of claim 1 , wherein each of the first phase-leg module, the second phase-leg module, and the third phase-leg module comprises a positive DC terminal and a negative DC terminal, an edge of the positive DC terminal being at least 1 centimeter (cm) apart horizontally from an edge of the negative DC terminal.

6. The assembly of claim 1 , wherein a top layer and a bottom layer of the layer stack do not comprise conductor layers coated with a solder mask.

7. The assembly of claim 1 , wherein the array of capacitors comprise low voltage capacitors, the array of capacitors connected in a parallel configuration to achieve a target capacitance.

8. The assembly of claim 1 , wherein, in the laminated motherboard, the first phase-leg module, the second phase-leg module, and the third phase-leg module comprise device static balancing resistors with embedded shielding, the embedded shielding configured to redistribute electric field distribution around a printed circuit board (PCB) surface of the laminated motherboard so that peak electric fields at triple points formed at interconnections of the PCB surface are mitigated.

9. The assembly of claim 1 , wherein:
the laminated motherboard further comprises a plated through hole (PTH) connected to a conductor layer among the plurality of conductor layers; and
net spacings with respect to the PTH of conductor layers not connected to the PTH among the plurality of conductor layers are based at least in part on a potential to be applied to the conductor layer connected to the PTH.

10. The assembly of claim 9 , wherein the net spacings of the conductor layers not connected to the PTH among the plurality of conductor layers are based at least in part on differences in potentials between potentials to be applied to each of the conductor layers not connected to the PTH as compared to the potential to be applied to the conductor layer connected to the PTH.

11. The assembly of claim 9 , further comprising embedded shielding implemented one layer in the layer stack below or above the PTH, the embedded shielding configured to redistribute electric field distribution around a printed circuit board (PCB) surface of the laminated motherboard so that peak electric fields at triple points formed at interconnections of the PCB surface are mitigated.

12. The assembly of claim 1 , wherein nodes between each of the plurality of distributed daughtercards are configured to connect to the plurality of connectors located on the bottom side of the laminated motherboard, the plurality of connectors corresponding to a plurality of electrical nets of the laminated motherboard.

13. The assembly of claim 12 , wherein each of the plurality of electrical nets corresponds to a different conductor layer of the plurality of conductor layers.

14. The assembly of claim 1 , wherein a MID conductor layer configured to have a mid-point potential among the plurality of conductor layers is spaced closest to a board edge or a non-plated through hole (NPTH) as compared to remaining conductor layers among the plurality of conductor layers, the remaining conductor layers being spaced from the board edge or the NPTH based at least in part on differences in potentials between potentials to be applied to each of the remaining conductor layers as compared to a potential to be applied to the MID conductor layer, the MID conductor layer configurable to be electrically grounded.

15. A laminated motherboard configured for a bus assembly, comprising:
a layer stack with a plurality of conductor layers;
a first phase-leg module, a second phase-leg module, and a third phase-leg module; and
a plated through hole (PTH) connected to a conductor layer among the plurality of conductor layers, wherein net spacings with respect to the PTH of conductor layers not connected to the PTH among the plurality of conductor layers are based at least in part on differences in potentials between potentials to be applied to each of the conductor layers not connected to the PTH as compared to a potential to be applied to the PTH.

16. The laminated motherboard of claim 15 , wherein the net spacings with respect to the PTH of each of the conductor layers not connected to the PTH increase as differences in potentials between potentials to be applied to each of the conductor layers not connected to the PTH as compared to a potential to be applied to the PTH increase.

17. The laminated motherboard of claim 15 , wherein each of the first phase-leg, the second phase-leg, and the third phase-leg comprises a plurality of device static balancing resistors with embedded shielding, the plurality of device static balancing resistors being mounted as surface mount (SMT) parts.

18. The laminated motherboard of claim 17 , wherein the embedded shielding is embedded one layer in the layer stack above or below the plurality of device static balancing resistors.

19. The laminated motherboard of claim 17 , wherein each of the plurality of device static balancing resistors with embedded shielding comprises individual embedded shielding.

20. The laminated motherboard of claim 15 , wherein a top layer and a bottom layer of the layer stack do not comprise conductor layers coated with a solder mask.

Assignees

• Virginia Tech Intellectual Properties Inc
• Virgina Tech Intellectual Properties Inc

Inventors

• Ravi Lakshmi
• Stewart Joshua
• Dong Dong
• Burgos Rolando

Classifications

• H02M7/5387

  in a bridge configuration · CPC title

• H02M1/327

  against abnormal temperatures · CPC title

• H05K3/429

  Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers · CPC title

• H05K2201/09718

  Clearance holes · CPC title

• H05K2201/09418

  Special orientation of pads, lands or terminals of component, e.g. radial or polygonal orientation · CPC title