On-package high-bandwidth resonant switched capacitor voltage regulator

Patent metadata

Field	Value
Publication number	US-11271475-B2
Application number	US-201916440901-A
Country	US
Kind code	B2
Filing date	Jun 13, 2019
Priority date	Jun 13, 2019
Publication date	Mar 8, 2022
Grant date	Mar 8, 2022

Abstract

Disclosed is an N:1 (where N is an integer such as 3 or higher) resonant star topology converter to generate an input supply (e.g., 1.8V) for a processor (e.g., a system-on-chip (SOC)) from a higher power supply source (e.g., 12.6V) such as a battery or other source. The resonant star topology based regulator can be realized by a combination of on-die and on-package components as opposed to voltage regulators on motherboard with discrete inductor and capacitors. In one example, capacitors of the N:1 resonant star topology are implemented as multilayer ceramic capacitors (MLCC). The architecture of the N:1 resonant star topology based regulator results in high bandwidth. For example, compared to traditional step-down voltage regulators, the N:1 resonant star topology based regulator exhibits ten times higher bandwidth.

First claim

What is claimed is:

1. An apparatus comprising:
a chain of at least four circuitries coupled in series, wherein each circuitry of the chain comprises:
first and second inverters coupled in parallel between a first power supply rail and a second power supply rail, wherein the first inverter is to receive a first clock, wherein the second inverter is to receive a second clock which is an inverse of the first clock, and wherein the first and second clocks are to toggle between voltages of the first and second power supply rails; and
a capacitor coupled to the first and second power supply rails;

a first set of inverters coupled between the second power supply rail of a last circuitry of the chain and ground, wherein each inverter of the first set of inverters is coupled to a corresponding first inverter of a circuitry of the chain via a first capacitor; and
a second set of inverters coupled between the second power supply rail of a last circuitry of the chain and ground, wherein each inverter of the second set of inverters is coupled to the second inverter of the corresponding circuitry of the chain via a second capacitor.

2. The apparatus of claim 1 , wherein each inverter of the first set is to receive a third clock, wherein each inverter of the second set is to receive a fourth clock which is an inverse of the third clock, wherein the third and fourth clocks are to toggle between voltages of the second power supply of a last circuitry of the chain and ground.

3. The apparatus of claim 2 , wherein phases of the third and fourth clocks are adjustable relative to phases of the first and second clocks.

4. The apparatus of claim 3 , further comprising a controller to control phases of the third and fourth clocks to regulate an output power supply.

5. The apparatus of claim 1 , further comprising a level-shifter coupled to the chain, wherein the level-shifter is to receive an input clock and to generate the first and second clocks from the input clock.

6. A system comprising:
a battery or a power supply;
a first voltage regulator comprising:
a chain of at least four circuitries coupled in series, wherein each circuitry of the chain comprises:
first and second inverters coupled in parallel between a first power supply rail and a second power supply rail, wherein the first inverter is to receive a first clock, wherein the second inverter is to receive a second clock which is an inverse of the first clock, wherein the first and second clocks are to toggle between voltages of the first and second power supply rails; and
a capacitor coupled to the first and second power supply rails; a first set of inverters coupled between the second power supply of a last circuitry of the chain and ground, wherein each inverter of the first set of inverters is coupled to a corresponding first inverter of a circuitry of the chain via a first capacitor; and
a second set of inverters coupled between the second power supply of a last circuitry of the chain and ground, wherein each inverter of the second set of inverters is coupled to the second inverter of a corresponding circuitry of the chain via a second capacitor;

a processor coupled to an output of the first voltage regulator, wherein the first voltage regulator is to provide a regulated input power supply to the processor; and
a memory coupled to the processor.

7. The system of claim 6 , wherein the processor includes a voltage regulator or a low dropout regulator that receive the regulated input power supply from the first voltage regulator.

8. The system of claim 6 , wherein each inverter of the first set is to receive a third clock, wherein each inverter of the second set is to receive a fourth clock which is an inverse of the third clock, and wherein the third and fourth clocks are to toggle between voltages of the second power supply of a last circuitry of the chain and ground.

9. The system of claim 8 , wherein phases of the third and fourth clocks are adjustable relative to phases of the first and second clocks.

10. The system of claim 8 , further comprising a controller to control phases of the third and fourth clocks to regulate an output power supply.

11. The system of claim 6 , wherein the first voltage regulator comprises a level-shifter coupled to the chain, and wherein the level-shifter is to receive an input clock and to generate the first and second clocks from the input clock.

Assignees

• Intel Corp

Inventors

• Jain Rinkle
• Douglas Jonathan
• Rajeurs Shivadarshan

Classifications

• H02M3/073 Primary

  Charge pumps of the Schenkel-type · CPC title

• H02M3/07 Primary

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H03K3/037

  Bistable circuits · CPC title

• G06F1/263

  Arrangements for using multiple switchable power supplies, e.g. battery and AC (G06F1/30 takes precedence) · CPC title

• H02M1/0058

  by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero (using an auxiliary actively switched resonant commutation circuit connected to an intermediate DC voltage or between two push-pull branches of an inverter bridge H02M7/4811; in resonant inverters H02M7/4815; in inverters operating from a resonant DC source H02M7/4826) · CPC title