Semiconductor devices

Patent metadata

Field	Value
Publication number	US-11270992-B2
Application number	US-202016992422-A
Country	US
Kind code	B2
Filing date	Aug 13, 2020
Priority date	Nov 5, 2019
Publication date	Mar 8, 2022
Grant date	Mar 8, 2022

Abstract

A semiconductor device includes standard cells disposed in a first direction parallel to an upper surface of a substrate and a second direction intersecting the first direction, each standard cell including an active region, a gate structure disposed to intersect the active region, source/drain regions on the active region at both sides of the gate structure, and first interconnection lines electrically connected to the active region and the gate structures; filler cells disposed between at least portions of the standard cells, each filler cell including a filler active region and a filler gate structure disposed to intersect the filler active region; and a routing structure disposed on the standard cells and the filler cells and including second interconnection lines electrically connecting the first interconnection lines of different standard cells to each other, wherein the second interconnection lines includes a first line having a first width and a second line having a second width larger than the first width.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a plurality of standard cells disposed in a first direction parallel to an upper surface of a substrate and a second direction intersecting the first direction, each standard cell from among the plurality of standard cells comprising an active region, a gate structure disposed to intersect the active region, a source region and a drain region disposed on the active region at either side of the gate structure, and a plurality of first interconnection lines electrically connected to the active region and the gate structure;
a plurality of filler cells disposed between portions of the plurality of standard cells, each filler cell from among the plurality of filler cells comprising a filler active region and a filler gate structure disposed to intersect the filler active region; and
a routing structure disposed on the plurality of standard cells and the plurality of filler cells, the routing structure comprising a plurality of second interconnection lines electrically connecting the respective plurality of first interconnection lines of different standard cells from among the plurality of standard cells to each other,
wherein the plurality of second interconnection lines comprises a first line having a first width and a second line having a second width larger than the first width.

2. The semiconductor device of claim 1 , wherein distances between centers of adjacent second interconnection lines from among the plurality of second interconnection lines is constant in a direction perpendicular to an extension direction of the plurality of second interconnection lines.

3. The semiconductor device of claim 2 ,
wherein the plurality of second interconnection lines comprises another first line having the first width,
wherein each second interconnection line from among the plurality of second interconnection lines comprises a region extending in the second direction, and the first line, the another first line and the second line of the second interconnection lines are sequentially arranged in the first direction, and
wherein a first distance between centers of the first line and the another first line adjacent each other is substantially equal to a second distance between centers of the another first line and the second line adjacent each other, in the first direction.

4. The semiconductor device of claim 1 , wherein the first line and the second line comprise signal transmission lines electrically connected to the source region and the drain region of a respective standard cell from among the plurality of standard cells.

5. The semiconductor device of claim 1 , wherein the first line and the second line comprise power transmission lines electrically connected to the source region and the drain region of a respective standard cell from among the plurality of standard cells.

6. The semiconductor device of claim 1 , wherein the second width is in a range of about 101% to about 125% of the first width.

7. The semiconductor device of claim 6 , wherein a difference between the first width and the second width is in a range of about 0.5 nm to about 6 nm.

8. The semiconductor device of claim 1 , wherein the second line comprises a first region having the first width and a second region having the second width.

9. The semiconductor device of claim 1 , wherein each standard cell from among the plurality of standard cells further comprises dummy gate structures disposed at both ends of the standard cell in the first direction.

10. The semiconductor device of claim 1 , wherein, in each standard cell from among the plurality of standard cells, the plurality of first interconnection lines comprises a third line having a third width and a fourth line having a fourth width larger than the third width.

11. The semiconductor device of claim 1 , wherein each standard cell from among the plurality of standard cells further comprises a first contact and a second contact connecting the plurality of first interconnection lines to the source region, the drain region and the gate structure, respectively, and
wherein the routing structure further comprises a plurality of vias connecting the plurality of first interconnection lines with the plurality of second interconnection lines.

12. The semiconductor device of claim 11 , wherein the routing structure further comprises a barrier layer disposed to be in contact with the plurality of second interconnection lines and the plurality of vias,
wherein the barrier layer extends toward a lower surface of the plurality of vias along side surfaces of the plurality of vias from side surfaces and lower surfaces of the plurality of second interconnection lines.

13. The semiconductor device of claim 1 , wherein the routing structure further comprises a plurality of third interconnection lines disposed on the plurality of second interconnection lines and electrically connected to the plurality of second interconnection lines,
wherein the plurality of third interconnection lines comprises a fifth line having a fifth width and a sixth line having a sixth width larger than the fifth width.

14. The semiconductor device of claim 1 , wherein each standard cell from among the plurality of standard cells further comprises a plurality of channel layers spaced apart from each other in a direction perpendicular to an upper surface of a respective active region, and
wherein the gate structure is configured to surround the plurality of channel layers.

15. A semiconductor device, comprising:
a first standard cell and a second standard cell disposed on a substrate, each of the first standard cell and the second standard cell comprising a semiconductor element and a first interconnection line electrically connected to the semiconductor element; and
a routing structure comprising a plurality of second interconnection lines extending in a direction across and on the first standard cell and the second standard cell, each second interconnection line from among the plurality of second interconnection lines electrically connecting the first interconnection line of the first standard cell to the first interconnection line of the second standard cell,
wherein the plurality of second interconnection lines comprises a first line and a second line having different widths from each other, and
wherein the first line and the second line comprise signal transmission lines transmitting a signal to the respective semiconductor elements of the first standard cell and the second standard cell.

16. The semiconductor device of claim 15 ,
wherein the plurality of second interconnection lines extend to be longer than each of the first standard cell and the second standard cell.

17. The semiconductor device of claim 16 , wherein the first interconnection line of each of the first standard cell and the second standard cell comprises a power transmission line supplying power to the semiconductor element.

18. The semiconductor device of claim 17 , wherein the plurality of second interconnection lines extend in a direction perpendicular to an extension line of the respective power transmission lines.

19. A semiconductor device, comprising:
a plurality of standard cells disposed on a substrate, each standard cell from among the plurality of standard cells comprising an active region, a gate structure disposed to intersect the active region, a source region and a drain region on the active region at either side of the gate structure, and a plurality of first interconnection lines electrically connected to the ac

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jaehoon
• Seomun Jun
• Lee Sua
• Kim Hyungock

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/495 Primary

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title