Memory system and method of operating the same

Patent metadata

Field	Value
Publication number	US-11270766-B2
Application number	US-202016928989-A
Country	US
Kind code	B2
Filing date	Jul 14, 2020
Priority date	Jan 2, 2020
Publication date	Mar 8, 2022
Grant date	Mar 8, 2022

Abstract

A memory system may include a memory device and a memory controller. The memory device may include memory cells. The memory controller may estimate and use an read voltage to distinguish one or more memory cells corresponding to a first threshold voltage distribution from one or more memory cells corresponding to a second threshold voltage distribution, the read voltage being estimated based on standard deviations and average threshold voltages of the first and the second threshold voltage distributions and probability density functions corresponding to the first and the second threshold voltage distributions, respectively. The memory controller may be structured and operable to calculate the standard deviation of the first threshold voltage distribution, based on a first probability area distinguished by a first target read voltage, a second probability area distinguished by a second target read voltage, and inverse Q-function values corresponding to the first and the second probability areas.

First claim

What is claimed is:

1. A memory system comprising:
a memory device including a plurality of memory cells; and
a memory controller configured to estimate and use a read voltage to distinguish one or more memory cells corresponding to a first threshold voltage distribution indicating first read-out data from one or more memory cells corresponding to a second threshold voltage distribution indicating second read-out data, the first and second threshold voltage distribution being adjacent to each other among a plurality of threshold voltage distributions corresponding to the memory cells, the read voltage being estimated based on standard deviations and average threshold voltages of the first and the second threshold voltage distributions and probability density functions corresponding to the first and the second threshold voltage distributions, respectively,
wherein the memory controller calculates the standard deviation of the first threshold voltage distribution, based on a first probability area corresponding to a first section of the first threshold voltage distribution distinguished by a first target read voltage, a second probability area corresponding to a second section of the first threshold voltage distribution distinguished by a second target read voltage, and inverse Q-function values respectively corresponding to the first and the second probability areas.

2. The memory system according to claim 1 , wherein the memory controller calculates the first and the second probability areas based on first read data and second read data received based on the first and the second target read voltages, respectively.

3. The memory system according to claim 2 , wherein the memory controller calculates the first and the second probability areas by comparing a preset number of memory cells corresponding to each of the plurality of threshold voltage distributions with a number of first bit values included in the first read data and the second read data.

4. The memory system according to claim 1 , wherein the memory controller calculates the standard deviation of the first threshold voltage distribution, based on a difference value between the first and the second target read voltages and a difference value between the inverse Q-function values respectively corresponding to the first and the second probability areas.

5. The memory system according to claim 1 , wherein the memory controller calculates the average threshold voltage of the first threshold voltage distribution, based on an inverse Q-function corresponding to any one of the first and the second probability areas and the standard deviation of the first threshold voltage distribution.

6. The memory system according to claim 1 , wherein the memory controller determines the first and the second target read voltages such that a difference value between the first and the second target read voltages is equal to or greater than a first threshold value.

7. The memory system according to claim 1 , wherein the memory controller determines the first and the second target read voltages such that a difference value between the first and the second probability areas is equal to or greater than a second threshold value.

8. The memory system according to claim 1 , wherein the memory controller determines the first and the second target read voltages such that each of the first and the second probability areas is within a preset threshold range.

9. The memory system according to claim 1 , wherein the memory controller calculates the standard deviation of the second threshold voltage distribution, based on a third probability area corresponding to a third section of the second threshold voltage distribution distinguished by a third target read voltage, a fourth probability area corresponding to a fourth section of the second threshold voltage distribution distinguished by a fourth target read voltage, and inverse Q-function values respectively corresponding to the third and the fourth probability areas.

10. The memory system according to claim 1 , wherein the memory controller calculates the standard deviation of the second threshold voltage distribution based on the standard deviation of the first threshold voltage distribution and a standard deviation ratio preset based on channel characteristics of the memory cells.

11. The memory system according to claim 10 , wherein the memory controller calculates the average threshold voltage of the second threshold voltage distribution, based on the standard deviation of the second threshold voltage distribution and an inverse Q-function value corresponding to a third probability area corresponding to a third section of the second threshold voltage distribution distinguished by a third target read voltage.

12. The memory system according to claim 10 , wherein the channel characteristics corresponds to at least one of a program/erase cycle and a retention time.

13. The memory system according to claim 1 ,
wherein the memory controller estimates the read voltage based on the average threshold voltage of the first threshold voltage distribution, a first weight corresponding to the average threshold voltage of the first threshold voltage distribution, the average threshold voltage of the second threshold voltage distribution, a second weight corresponding to the average threshold voltage of the second threshold voltage distribution, and an offset value, and
wherein the first weight, the second weight, and the offset value are preset based on channel characteristics of the memory cells.

14. The memory system according to claim 1 , wherein the memory controller estimates the read voltage based on an approximation using the probability density functions.

15. The memory system according to claim 14 ,
wherein the approximation is obtained based on the average threshold voltage of the first threshold voltage distribution, a first weight corresponding to the average threshold voltage of the first threshold voltage distribution, the average threshold voltage of the second threshold voltage distribution, and a second weight corresponding to the average threshold voltage of the second threshold voltage distribution, and
wherein the first weight and the second weight are preset based on channel characteristics of the memory cells.

16. The memory system according to claim 15 , wherein the approximation is associated with an offset value preset based on the channel characteristics of the memory cells.

17. The memory system according to claim 1 , wherein the threshold voltage distributions have Gaussian distribution characteristics or distribution characteristics close to a Gaussian distribution.

18. The memory system according to claim 1 , wherein the memory controller performs a read operation on the memory cells using the estimated read voltage.

19. A method of operating a memory system comprising:
calculating standard deviations and average threshold voltages of first and second threshold voltage distributions, the first threshold voltage distribution corresponding to memory cells storing first read-out data, the second threshold voltage distribution corresponding to memory cells storing second read-out data, a number of memory cells for first and second read-out data being expressed as a function of the threshold voltage to obtain first and second threshold voltage distribution, the first and second threshold voltage distribution being adjacent to each other among a plurality of threshold voltage distributions corresponding to a plurality of memory cells; and
estimating a read vol

Assignees

• Sk Hynix Inc

Inventors

• Kim Dae Sung
• Kim Kyung Bum

Classifications

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/30

  Power supply circuits · CPC title

• G11C16/349

  Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles · CPC title

• G11C7/00

  Arrangements for writing information into, or reading information out from, a digital store (G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413) · CPC title

• G11C11/5671

  using charge trapping in an insulator · CPC title