Shift register unit and driving method thereof, gate drive circuit and display device

Patent metadata

Field	Value
Publication number	US-11270623-B2
Application number	US-201816335752-A
Country	US
Kind code	B2
Filing date	Aug 15, 2018
Priority date	Jan 2, 2018
Publication date	Mar 8, 2022
Grant date	Mar 8, 2022

Abstract

A shift register unit and a driving method therof, a gate drive circuit and a display device are disclosed. The shift register unit includes an input circuit, a reset circuit, a first anti-leakage circuit and an output circuit. Because the signal of the pull-up node is provided to the first node and the second node by the first anti-leakage circuit, internal potential difference among the input circuit, the reset circuit, and the first anti-leakage circuit is relatively small, the input circuit is connected with the pull-up node, the reset circuit is connected with the pull-up node and the second node simulatneously, and the first anti-leakage circuit is connected with the first node, the pull-up node and the second node simultaneously.

First claim

What is claimed is:

1. A shift register unit, comprising an input circuit, a reset circuit, a first anti-leakage circuit and an output circuit,
wherein the input circuit is connected with a first signal input terminal, a first node and a first level control node, and configured for providing a signal of the first signal input terminal to the first level control node via the first node under control of the first signal input terminal;
the reset circuit is connected with a second signal input terminal, a first voltage input terminal, a second node and the first level control node, and configured for providing a signal of the first voltage input terminal to the first level control node via the second node under control of the second signal input terminal;
the first anti-leakage circuit is connected with the first level control node, the first node and the second node, and configured for providing a signal of the first level control node to the first node and the second node under control of the first level control node; and
the output circuit is connected with the first level control node, a first clock signal input terminal and a signal output terminal, and configured for providing a signal of the first clock signal input terminal to the signal output terminal under control of the first level control node.

2. The shift register unit claimed as claim 1 , wherein the input circuit includes a first switch transistor,
a gate electrode of the first switch transistor is connected to the first signal input terminal, a first electrode of the first switch transistor is connected to the first signal input terminal via the first node, and a second electrode of the first switch transistor is connected to the first level control node.

3. The shift register unit claimed as claim 1 , wherein the reset circuit Rides a second switch transistor and a third switch transistor,
a gate electrode of the second switch transistor is connected to the second signal input terminal, a first electrode of the second switch transistor is connected to the second node, and a second electrode of the second switch transistor is connected to the first voltage input terminal; and
a gate electrode of the third switch transistor is connected o the second signal input terminal, a first electrode of the third switch transistor is connected to the first level control node, and a second electrode of the third switch transistor is connected to the second node.

4. The shift register unit claimed as claim 1 , wherein the first anti-leakage circuit includes a fourth switch transistor and a fifth switch transistor,
both a gate electrode and a first electrode of the fourth switch transistor are connected with the first level control node, and a second electrode of the fourth switch transistor is connected to the first node; and
both a gate electrode and a second electrode of the fifth switch transistor are connected with the first level control node, and a first electrode of the fifth switch transistor is connected to the second node.

5. The shift register unit claimed as claim 1 , wherein the output circuit includes a sixth switch transistor and a capacitor,
a gate electrode of the sixth switch transistor is connected with the first first level control node, a first electrode of the sixth switch transistor is connected to the first clock signal input terminal, and a second electrode of the sixth switch transistor is connected to the signal output terminal; and
one end of the capacitor is connected to the first level control node, and other end of the capacitor is connected to the signal output terminal.

6. The shift register unit claimed as claim 1 , further comprising a first pull-blown circuit,
wherein the first pull-down circuit is connected with a second clock signal input terminal, the first voltage input terminal, the third node and the signal output terminal, and configured for supplying the signal of the first voltage input terminal to the signal output terminal via the third node under control of the second clock signal input terminal.

7. The shift register unit claimed as claim 6 , wherein the first pull-down circuit includes a seventh switch transistor and an eighth switch transistor,
a gate electrode of the seventh switch transistor is connected to the second clock signal input terminal, a first electrode of the seventh switch transistor is connected to the third node, and a second electrode of the seventh switch transistor is connected to the first voltage input terminal; and
a gate electrode of the eighth switch transistor is connected to the second clock signal input terminal, a first electrode of the eighth switch transistor is connected to the signal output terminal, and the second electrode of the eighth switch transistor is connected to the third node.

8. The shift register unit claimed as claim 6 , further comprising a second pull-down circuit,
wherein the second pull-down circuit is connected to the signal output terminal and the third node, and configured for providing a signal of the signal output terminal to the third node under control of the signal output terminal.

9. The shift register unit claimed as claim 8 , wherein the second pull-down circuit includes a ninth switch transistor,
both a gate electrode and a second electrode of the ninth switch transistor are connected to the signal output terminal, and a first electrode of the ninth switch transistor is connected to the third node.

10. The shift register unit claimed as claim 6 , further comprising a signal-output-terminal de-noising circuit, a pull-up-node de-noising circuit, a pull-down-node first control circuit, a pull-down-node second control circuit and a pull-down-node third control circuit,
wherein the signal-output-terminal de-noising circuit is connected with the third node, the signal output terminal and a second level control node, and configured to supply the signal of the signal output terminal to the third node under control of the second level control node;
the pull-up-node de-noising circuit is connected with the first level control node, the second node and the second level control node, and configured to supply the signal of the first level control node to the second node under control of the second level control node;
the pull-down-node first control circuit is connected with the first signal input terminal, the first level control node, the second level control node and the first voltage input terminal, and configured for supplying the signal of the first voltage input terminal to the second level control node under control of one selected from the group consisting of the first signal input terminal and the first level control node;
the pull-down-node second control circuit is connected with a third clock signal input terminal, the second level control node and the first voltage input terminal, and configured for supplying the signal of the first voltage input terminal to the second level control node under control of the third clock signal input terminal; and
the pull-down-node third control circuit is connected with a fourth clock signal input terminal and the second level control node, and configured for providing a signal of the fourth clock signal input terminal to the second level control node under control of the fourth clock signal input terminal.

11. A gate drive circuit, comprising a plurality of cascaded shift register units each as claim 1 , wherein
a first signal input terminal of a shift register unit at a first level is connected with a frame trigger signal terminal;
except for the shift register unit at the first level, a first signal input terminal of a shift register unit at each of the remaining levels is

Assignees

• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Hu Qi
• Jing Hui
• Liao Weijing

Classifications

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2320/0219

  Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling · CPC title

• G09G3/2092 Primary

  Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165) · CPC title