Memory system for preventing write error

Patent metadata

Field	Value
Publication number	US-11269721-B2
Application number	US-202016884377-A
Country	US
Kind code	B2
Filing date	May 27, 2020
Priority date	Jan 11, 2017
Publication date	Mar 8, 2022
Grant date	Mar 8, 2022

Abstract

A memory system apparatus may be provided. The memory system may have memory controller. The memory controller may be configured to perform a scrambling operation before an error correction code (ECC) operation is performed.

First claim

What is claimed is:

1. A memory system comprising:
a memory controller configured to receive original data from host and transmit recovered data to the host; and
a memory device configured to store encoded data received from the memory controller, and to output read data in responding to a read command which is received from the memory controller,
wherein the memory controller comprising:
a scrambler configured to randomize the original data to generate scrambled data;
a scrambling selector configured to select and output the original data or scrambled data based on randomness of the original data;
an error correction code (ECC) encoder configured to perform an ECC encoding operation of the output data of the scrambling selector;
an ECC decoder configured to perform an ECC decoding operation of the read data to generate decoded data; and
a descrambler configured to descramble the decoded data to generate descrambled data having the same bit sequence as the original data; and
a descrambling selector configured to select the recovered data among the descrambled data and the decoded data based on the selection of the scrambling selector.

2. The memory system of claim 1 , wherein the scrambler includes:
a shift register configured to have a plurality of storage elements;
a first exclusive OR (XOR) arithmetic element configured to perform an XOR operation of data stored in two storage elements among the plurality of storage elements to output the result of the XOR operation; and
a second XOR arithmetic element configured to perform an XOR operation of an output datum of the first XOR arithmetic element and one datum among a plurality of bit data of the original data to output the result of the XOR operation,
wherein the plurality of bit data of the original data are sequentially inputted to the second XOR arithmetic element.

3. The memory system of claim 2 , wherein an output datum of the second XOR arithmetic element is fed back to and stored into a first storage element of the shift register.

4. The memory system claim 2 , wherein an output datum of the second XOR arithmetic element is used as one among a plurality of bit data constituting the scrambled data.

5. A memory system comprising:
a memory controller configured to receive original data from host and transmit recovered data to the host; and
a memory device configured to store encoded data received from the memory controller, and output read data in responding to a read command which is received from the memory controller,
wherein the memory controller comprising:
a memory configured to store the recovered data;
a scrambling engine configured to randomize original data to generate scrambled data;
a scrambling selector configured to select and output the original data or scrambled data based on randomness of the original data;
an error correction code (ECC) encoder configured to perform an ECC encoding operation of the output of the scrambling selector;
an ECC decoder configured to perform an ECC decoding operation of the read data to generate decoded data;
a descrambling selector configured to output the decoded data to the scrambling engine or the memory based on the selection of the scrambling selector; and
wherein the scrambling engine configured to descramble decoded data of the descrambling selector to generate the recovered data having the same bit sequence as the original data if the descrambling selector outputs the decoded data to the scrambling engine.

6. The memory system of claim 5 , wherein the descrambling selector connects to the memory.

7. The memory system of claim 5 , wherein the second route directly connects the descrambling selector is connected to an external device disposed at an outside region of the memory controller.

Assignees

• Sk Hynix Inc

Inventors

• Kim Soojin

Classifications

• G06F12/0238

  Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory · CPC title

• H03M13/13

  Linear codes · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G06F9/30029

  Logical and Boolean instructions, e.g. XOR, NOT · CPC title