Method for testing solder balls between two substrates by using dummy solder balls

Patent metadata

Field	Value
Publication number	US-11269020-B2
Application number	US-201916726147-A
Country	US
Kind code	B2
Filing date	Dec 23, 2019
Priority date	Dec 27, 2018
Publication date	Mar 8, 2022
Grant date	Mar 8, 2022

Abstract

A plurality of test pads are formed on a first substrate or a second substrate. A plurality of first solder joints are reserved on a first surface of the first substrate, and each of the first solder joints is coupled to at least a test pad or to another first solder joint through at least a first trace. A plurality of second solder joints are reserved on a second surface of the second substrate. Each of the second solder joints is coupled to at least a test pad or to another second solder joint through at least a second trace. A plurality of dummy solder balls are formed between the first solder joints and the second solder joints. Probes are coupled to the test pads to measure circuit characteristics between the test pads.

First claim

What is claimed is:

1. A method of testing a plurality of solder balls between a first substrate and a second substrate, the first substrate comprising a plurality of first traces and a first integrated circuit, the second substrate comprising a plurality of second traces and a second integrated circuit, a plurality of test pads being formed on the first substrate or the second substrate and being electrically disconnected from the first integrated circuit and the second integrated circuit, the method comprising:
reserving a plurality of first solder joints on a first surface of the first substrate, each of the first solder joints being coupled to at least a test pad or to another first solder joint through at least a first trace;
reserving a plurality of second solder joints on a second surface of the second substrate, the second surface facing the first surface, and each of the second solder joints being coupled to at least a test pad or to another second solder joint through at least a second trace;
forming a plurality of dummy solder balls between the plurality of first solder joints and the plurality of second solder joints, wherein the dummy solder balls are electrically disconnected from the first integrated circuit and the second integrated circuit; and
coupling a plurality of probes to the plurality of test pads to measure circuit characteristics between the plurality of test pads.

2. The method of claim 1 , wherein the circuit characteristics between the test pads comprise a resistance value between any two of the test pads.

3. The method of claim 1 , wherein the circuit characteristics between the test pads comprise a current flowing through any two of the test pads.

4. The method of claim 1 , wherein the test pads are all formed on the first substrate.

5. The method of claim 1 , wherein the test pads are all formed on the second substrate.

6. The method of claim 1 , wherein some of the test pads are formed on the first substrate, and remaining test pads are formed on the second substrate.

7. The method of claim 1 , wherein some of the test pads are formed on the second surface of the second substrate.

8. The method of claim 1 , wherein a plurality of through holes are formed in the second substrate, and some of the second traces are formed in the through holes.

9. The method of claim 8 , wherein the through holes are formed between a third surface of the second substrate and the second surface, and some of the test pads are formed on the third surface.

10. The method of claim 1 , wherein the first substrate further comprises a plurality of third solder joints, the second substrate further comprises a plurality of fourth solder joints, the third solder joints are coupled to the first integrated circuit, the fourth solder joints are coupled to the second integrated circuit, the test pads are electrically disconnected from the third solder joints, and the fourth solder joints, and a plurality of solder balls are formed between the third solder joints and the fourth solder joints to couple the first integrated circuit to the second integrated circuit.

11. The method of claim 10 , wherein an average distance of the first solder joints from a center of the first substrate is greater than an average distance of the third solder joints from the center of the first substrate, and an average distance of the second solder joints from a center of the second substrate is greater than an average distance of the fourth solder joints from the center of the second substrate.

Assignees

• Qisda Corp

Inventors

• Wu Po-Fu

Classifications

• G01R31/2853

  Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections (G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66) · CPC title

• G01R31/2896 Primary

  Testing of IC packages; Test features related to IC packages (containers per se H10W76/10, encapsulations per se H10W74/00) · CPC title

• G01R1/0408

  Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets (G01R1/067 takes precedence; mass production testing systems G01R31/59; testing of connections G01R31/66; for testing printed circuit boards G01R31/2808) · CPC title

• G01R31/71 Primary

  Testing of solder joints · CPC title

• G01R1/06

  Measuring leads; Measuring probes (G01R19/145, G01R19/165 take precedence) · CPC title