Multi-channel scalable EEG acquisition system on a chip with integrated patient specific seizure classification and recording processor

Patent metadata

Field	Value
Publication number	US-11266340-B2
Application number	US-201815955010-A
Country	US
Kind code	B2
Filing date	Apr 17, 2018
Priority date	Feb 17, 2012
Publication date	Mar 8, 2022
Grant date	Mar 8, 2022

Abstract

An integrated circuit chip and method for EEG monitoring. In one embodiment, the integrated circuit chip includes an Analog Front End cell in communication with an electrode and a Classification Processor wherein a signal received from the electrode is processed by the Classification Engine cell and designated as seizure or non-seizure. In another embodiment, the Analog Front End cell includes an amplifier cell in communication with an electrode; and an ASPU cell in communication with the amplifier cell. In yet another embodiment, the Classification Processor includes a DBE Channel Controller cell; a Feature Extraction Engine Processor cell, and a Classification Engine cell in communication with the Feature Extraction Engine Processor cells and the DBE Channel Controller cell.

First claim

The invention claimed is:

1. An electroencephalogram (EEG) monitor, comprising:
an integrated circuit chip comprising:
an Analog Front End cell, the Analog Front End cell comprising:
an amplifier cell in communication with an EEG electrode;
an analog signal processing unit (ASPU) cell in communication with the amplifier cell; and
a Classification Processor comprising:

a digital back end (DBE) Channel Controller cell;
a Feature Extraction Engine Processor cell, the Feature Extraction Engine Processor cell in communication with the DBE Channel Controller cell and the Analog Front End cell; and
a Classification Engine cell in communication with the Feature Extraction Engine Processor cell and the DBE Channel Controller cell; and
wherein a signal received from the electrode is processed by the Classification Engine cell and designated as seizure or non-seizure.

2. The EEG Monitor of claim 1 wherein the amplifier cell in communication with the electrode is a Chopper Stabilized-Capacitive Coupled Instrumentation Amplifier (CS-CCIA) cell.

3. The EEG Monitor of claim 1 wherein the amplifier cell in communication with the electrode is an autozeroing amplifier circuit cell.

4. The EEG Monitor of claim 1 wherein the Feature Extraction Engine Processor cell comprises:
a plurality of bandpass filter cells, each bandpass filter cell in communication with the ASPU cell; and
a plurality of integrator cells, each integrator cell in communication with a respective one of the plurality of bandpass filter cells;
wherein a signal from the ASPU cell of an Analog Front End is filtered by a plurality of bandpass filters to form a plurality of sub-bands, and
wherein each of the sub-bands is integrated by a respective one of the plurality of integrator cells to determine the energy of the sub-band.

5. The EEG Monitor of claim 4 wherein the Feature Extraction Engine Processor cell further comprises:
a decimation filter cell in communication between the ASPU cell and the plurality of bandpass filter cells; and
wherein a signal from the ASPU cell of an Analog Front End is decimated by the decimation cell prior to being filtered by the plurality of bandpass filter cells.

6. The EEG Monitor of claim 4 wherein the integrated sub-bands are aggregated to form a feature vector.

7. The EEG Monitor of claim 6 wherein the Classification Engine cell designates the signal received from the electrode as a seizure condition or a non-seizure condition in response to the feature vector.

8. The EEG Monitor of claim 1 , wherein the integrated circuit chip further comprising an analog to digital converter cell in communication with the ASPU cell and the Feature Extraction Engine Processor cell.

9. The EEG Monitor of claim 8 wherein the analog to digital converter cell in communication with the ASPU cell and the Feature Extraction Engine Processor cell is a Successive-approximation-register analog-to-digital converters (SAR ADC).

10. The EEG Monitor of claim 7 wherein the Classification Engine comprises a support vector machine (SVM) and the SVM designates the signal, received from the electrode, as seizure or non-seizure in response to the feature vector, by determining on which side of a hyperplane in feature hyperspace the feature vector lies.

11. The EEG Monitor of claim 1 :
wherein the Analog Front End cell is a plurality of Analog Front End cells,
wherein the Feature Extraction Engine cell is a plurality of Feature Extraction Engine cells, and
wherein each Feature Extraction Engine cell is in communication with a respective one of the Analog Front End cells.

12. The EEG Monitor of claim 11 , wherein the integrated circuit chip further comprising:
a multiplexer cell in communication with the plurality of Analog Front End cells; and
an analog to digital converter (ADC) cell in communication with the multiplexer cell and the plurality of Feature Extraction Engine Processor cells.

13. The EEG Monitor of claim 12 , where the ADC cell is a successive approximation register (SAR) cell.

14. The EEG Monitor of claim 1 wherein the DBE Channel controller comprises:
a channel gain control line and a channel bandwidth control line in communication with an Analog Front End cell.

15. The EEG Monitor of claim 12 wherein the DBE Channel Controller comprises:
a channel gain control line, a channel bandwidth control line, and a channel number select in communication with the Analog Front End (AFE) Channel Controllers and a channel select control line in communication with the multiplexer cell,
wherein the DBE Channel Controller is in communication with an external data interface, and
wherein the DBE Channel Controller selects the number of channel to be used in response to receiving the number of channels from the external data interface and setting the respective AFE Channel Controller on or off.

16. The EEG Monitor of claim 4 , wherein each bandpass filter comprises:
a plurality of Look Up Tables (LUTs), each LUT having a plurality of inputs and having an output,
a plurality of bit shift registers, each bit shift register having an input in communication with the ASPU and an output in communication with a respective input of the LUT;
a summer having a first input in communication with the output of the LUT and having a second input and an output; and
a register having an input in communication with the output of the summer and having an output in communication with the second input of the summer;
wherein the output of the bandpass filter is the output of the register.

17. The EEG Monitor of claim 16 wherein the LUT is a distributed quad-LUT.

18. The EEG Monitor of claim 2 wherein the CS-CCIA comprises:
an input-chopped switch having an input in communication with the electrode and having an output;
a low noise amplifier having an input in communication with the output of the input-chopped switch and a first output connected to an input of the ASPU and having a second output;
an Impedance Boosting Loop (IBL) comprising a IBL chopper switch having an input in communication with the low noise amplifier output and an output in communication with the low noise amplifier input;
a direct current (DC) Servo Loop comprising:
a DC Servo Loop (DSL) amplifier having an input in communication with the output of the low noise amplifier;
a DSL chopper switch having an input in communication with the output of the DSL amplifier and a output in communication with the input of the low noise amplifier; and
an Offset Cancellation Loop (OCL) comprising:
an OCL amplifier having an input in communication with the second output of the low noise amplifier and having an output;
an OCL chopped switch having an input in communication with the output of the OCL amplifier and having an output;
a high pass filter having an input in communication with the output of the OCL chopped switch and having an output; and
a gain chopped switch having an input in communication with the output of the high pass filter and having an output in communication with the input of the low noise amplifier.

19. The EEG Monitor of claim 3 wherein the autozeroing amplifier circuit cell comprises:
an auto zero amplifier having an input in communication with the electrode and having an output;
a low noise amplifier having an input in communication with the output of the autozero amplifier and a first output connected to an input of the ASPU and having a second output;
an Impedance Boosting Loop (IBL) comprising a IBL chopper switch having an input in communication with the

Assignees

• Massachusetts Inst Technology
• Univ Khalifa Science & Technology

Inventors

• Yoo Jerald
• Chandrakasan Anantha P
• Yan Long
• El-Damak Dina Reda
• Shoeb Ali Hossam
• Bin Altaf Muhammad Awais

Classifications

• A61B5/384

  Recording apparatus or displays specially adapted therefor · CPC title

• A61B5/372 Primary

  Analysis of electroencephalograms · CPC title

• A61B5/4094 Primary

  Diagnosing or monitoring seizure diseases, e.g. epilepsy · CPC title

• A61B5/369

  Electroencephalography [EEG] · CPC title

• A61B2562/166

  the sensor is mounted on a specially adapted printed circuit board · CPC title