Physically unclonable camouflage structure and methods for fabricating same

Patent metadata

Field	Value
Publication number	US-11264990-B2
Application number	US-202016775077-A
Country	US
Kind code	B2
Filing date	Jan 28, 2020
Priority date	Feb 24, 2009
Publication date	Mar 1, 2022
Grant date	Mar 1, 2022

Abstract

An application specific integrated circuit (ASIC) and a method for its design and fabrication is disclosed. In one embodiment, the camouflaged application specific integrated circuit (ASIC), comprises a plurality of interconnected functional logic cells that together perform one or more ASIC logical functions, wherein the functional logic cells comprise a camouflage cell including: a source region of a first conductivity type, a drain region of the first conductivity type, and a camouflage region of a second conductivity type disposed between the source region and the drain region. The camouflage region renders the camouflage cell always off in a first camouflage cell configuration and always on in a second camouflage cell configuration having a planar layout substantially indistinguishable from the first configuration.

First claim

What is claimed is:

1. A camouflaged application specific integrated circuit (ASIC), comprising:
a plurality of interconnected functional logic cells that together perform one or more ASIC logical functions;
wherein the plurality of interconnected functional logic cells comprise:
an uncamouflaged functional cell having two spaced apart implanted regions, the uncamouflaged functional cell performing a first functional logic cell function and having a first planar layout; and
a camouflaged functional cell having two spaced apart implanted further regions, the camouflaged functional cell performing a second functional logic cell function and having a second planar layout; wherein:
a first region of the two spaced apart implanted further regions comprises a source region of a first conductivity type;
a second region of the two spaced apart implanted further regions comprises a drain region of the first conductivity type:
the camouflaged functional cell further comprises an implanted camouflage region disposed between the source region and the drain region and is of a second conductivity type; and
the camouflaged functional cell further comprises a gate; and
wherein the implanted camouflage region is configured to create or prevent a conduction channel between the source region and the drain region independent of a gate voltage at the gate.

2. The ASIC of claim 1 , wherein the implanted camouflage region comprises a lightly doped region of the second conductivity type.

3. The ASIC of claim 2 , wherein:
the first planar layout is of same physical dimensions as the second planar layout; and
the implanted camouflage region is configured to prevent the conduction channel between the source region and the drain region independent of the gate voltage.

4. The ASIC of claim 3 , wherein:
the source region and the drain region are disposed in a well region;
the implanted camouflage region comprises a source camouflage region adjacent the source region and a drain camouflage region adjacent the drain region; and
the camouflaged functional cell further comprises:
a conductive layer, having a source conductive layer portion disposed in conductive contact with the source region and a drain conductive layer portion disposed in conductive contact with the drain region, wherein:
the source conductive layer portion is conductively isolated from the source camouflage region and the drain conductive layer portion is conductively isolated from the drain camouflage region.

5. The ASIC of claim 3 , wherein the implanted camouflage region renders the camouflaged functional cell always off.

6. The ASIC of claim 2 , wherein:
the first planar layout is of substantially the same physical dimensions as the second planar layout; and
the implanted camouflage region is configured to create the conduction channel between the source region and the drain region independent of the gate voltage.

7. The ASIC of claim 6 , wherein the implanted camouflage region renders the camouflaged functional cell always on.

8. The ASIC of claim 7 , wherein:
the source region and the drain region are disposed in a well region;
the implanted camouflage region comprises a source camouflage region adjacent the source region and a drain camouflage region adjacent the drain region; and
the camouflaged functional cell further comprises:
a conductive layer, having a source conductive layer portion disposed in conductive contact with the source region and a drain conductive layer portion disposed in conductive contact with the drain region, wherein:
the source conductive layer portion is in conductive contact with the source camouflage region and the drain conductive layer portion is in conductive contact with the drain camouflage region.

9. The ASIC of claim 1 , wherein the camouflaged functional cell forms at least a portion of a logic buffer.

10. The ASIC of claim 1 , wherein:
at least a subset of the interconnected functional logic cells together comprise one or more of:
a one-time programmable logic circuit having the camouflaged functional cell;
a field programmable gate array configuration manager block having the camouflaged functional cell:
a memory controller having the camouflaged functional cell:
a challenge-response authentication function containing the camouflaged functional logic to compute on-chip encryption keys containing the camouflaged functional cell:
on-chip identifiers containing the camouflaged functional cell:
analog or mixed-signal processing circuitry containing the camouflaged functional a field programmable gate array configuration manager block having the camouflaged functional cell:
a memory controller having the camouflaged functional cell;
a challenge-response authentication function containing the camouflaged functional cell;
a logic circuit having a plurality of inputs and a logical circuit output; and
a one-time programmable circuit having a one-time programmable circuit output communicatively coupled to at least one of the plurality of inputs, the one-time programmable circuit further comprising the camouflaged functional cell.

11. A method of camouflaging an application specific integrated circuit (ASIC), comprising:
defining a plurality of interconnected functional logic cells that together perform one or more ASIC logical functions, wherein the plurality of interconnected functional logic cells comprise:
an uncamouflaged functional cell having two spaced apart implanted regions, the uncamouflaged functional cell performing a first functional logic cell function and having a first planar layout;
a camouflaged functional cell having two spaced apart implanted further regions, the camouflaged functional cell performing a second functional logic cell function different from the first functional logic cell function and having a second planar layout; wherein:
a first region of the two spaced apart implanted regions further comprises a source region of a first conductivity type:
a second region of the two spaced apart implanted further regions comprises a drain region of the first conductivity type:
the camouflaged functional cell further comprises an implanted camouflage region disposed between the source region and the drain region and is of a second conductivity type; and
the camouflaged functional cell further comprises a gate:
wherein the implanted camouflage region is configured to create or prevent a conduction channel between the source region and the drain region independent of a gate voltage at the gate; and

defining a routing of the plurality of interconnected functional logical cells, including the camouflaged functional cell.

12. The method of claim 11 , wherein the implanted camouflage region comprises a lightly doped region of the second conductivity type.

13. The method of claim 12 , wherein:
the first planar layout is of same physical dimensions as the second planar layout; and
the implanted camouflage region is configured to prevent the conduction channel between the source region and the drain region independent of the gate voltage.

14. The method of claim 13 , wherein the implanted camouflage region renders the camouflaged functional cell always off.

15. The method of claim 14 , wherein:
the source region and the drain region are disposed in a well region;
the implanted camouflage region comprises a source camouflage region adjacent the source region and a drain camouflage region adjacent the drain region; and
the camouflaged functional cell further comprises:
a conductive layer, having a source conductive layer portion disposed in conductive contact

Assignees

• Rambus Inc

Inventors

• Cocchi Ronald P
• Chow Lap Wai
• Baukus James P
• Wang Bryan J

Classifications

• H10D84/907

  CMOS gate arrays · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• G06F30/30

  Circuit design · CPC title

• G06F21/14

  against software analysis or reverse engineering, e.g. by obfuscation · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title